ELEC 5270/6270 Spring 2009 Low-Power Design of Electronic Circuits Pseudo-nMOS, Dynamic CMOS and Domino CMOS Logic Vishwani D. Agrawal James J. Danaher Professor Dept. of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 vagrawal@eng.auburn.edu http://www.eng.auburn.edu/~vagrawal/COURSE/E6270_Spr09/course.html Copyright Agrawal, 2007 ELEC6270 Spring 09, Lecture 15

Why Not Static CMOS? Advantages: Static (robust) operation, low power, scalable with technology. Disadvantages: Large size: An N input gate requires 2N transistors. Large capacitance: Each fanout must drive two devices. Alternatives: Pass-transistor logic (PTL), pseudo-nMOS, dynamic CMOS, domino CMOS. Copyright Agrawal, 2007 ELEC6270 Spring 09, Lecture 15

A Pseudo-nMOS Gate VDD VDD PUN Output Output PDN PDN Inputs Inputs CMOS Gate Pseudo-nMOS Gate Copyright Agrawal, 2007 ELEC6270 Spring 09, Lecture 15

Pseudo-nMOS NOR VDD Output Input 2 Input 3 Input 1 Copyright Agrawal, 2007 ELEC6270 Spring 09, Lecture 15

Pseudo-nMOS NAND VDD Output Input 1 Input 2 Copyright Agrawal, 2007 ELEC6270 Spring 09, Lecture 15

Pseudo-nMOS Inverter VDD Output Input Copyright Agrawal, 2007 ELEC6270 Spring 09, Lecture 15

Inverter Characteristics 3.0 2.5 2.0 1.5 1.0 0.5 0.0 Nominal device: W 0.5μ ── = ──── = 2 Ln 0.25μ W/Lp = 4 Output voltage, V W/Lp = 0.5 W/Lp = 1 W/Lp = 2 W/Lp = 0.25 0.0 0.5 1.0 1.5 2.0 2.5 Input voltage, V Copyright Agrawal, 2007 ELEC6270 Spring 09, Lecture 15

Performance of Inverter Size, W/Lp Logic 0 voltage Logic 0 static power Delay 0 → 1 4 0.693 V 564 μW 14 ps 2 0.273 V 298 μW 56 ps 1 0.133 V 160 μW 123 ps 0.5 0.064 V 80 μW 268 ps 0.25 0.031 V 41 μW 569 ps J. M. Rabaey, A. Chandrakasan and B. Nokolić, Digital Integrated Circuits, Upper Saddle River, New Jersey: Pearson Education, 2003, page 262. Copyright Agrawal, 2007 ELEC6270 Spring 09, Lecture 15

Negative Aspects of Pseudo-nMOS Output 0 state is ratioed logic. Faster gates mean higher static power. Low static power means slow gates. Copyright Agrawal, 2007 ELEC6270 Spring 09, Lecture 15

A Dynamic CMOS Gate VDD Precharge transistor Output PDN Inputs CL Evaluate transistor CK Copyright Agrawal, 2007 ELEC6270 Spring 09, Lecture 15

Two-Phase Operation in a Vector Period CK Inputs Output Precharge low don’t care high Evaluation Valid inputs Valid outputs Copyright Agrawal, 2007 ELEC6270 Spring 09, Lecture 15

4-Input NAND Dynamic CMOS Gate VDD CK A B C D Output = CK’ + (ABCD)’∙ CK CL tL→H ≈ 0 Copyright Agrawal, 2007 ELEC6270 Spring 09, Lecture 15

Characteristics of Dynamic CMOS Nonratioed logic – sizing of pMOS transistor is not important for output levels. Smaller number of transistors, N+2 vs. 2N. Larger precharge transistor reduces output fall time, but increases precharge power. Faster switching due to smaller capacitance. Static power – negligible. Short-circuit power – none. Dynamic power no glitches – following precharge, signals can either make transitions only in one direction, 1→0, or no transition, 1→1. only logic transitions – all nodes at logic 0 are charged to VDD during precharge phase. Copyright Agrawal, 2007 ELEC6270 Spring 09, Lecture 15

Switching Speed and Power Fewer transistors mean smaller node capacitance. No short-circuit current to slow down discharging of capacitance. Only dynamic power consumed, but can be higher than CMOS. Copyright Agrawal, 2007 ELEC6270 Spring 09, Lecture 15

Logic Activity Probability of 0 → 1 transition: Static CMOS, p0 p1 = p0(1 – p0) Dynamic CMOS, p0 ≥ p0 p1 Example: 2-input NOR gate Static CMOS, Pdyn = 0.1875 CLVDD2fCK Dynamic CMOS, Pdyn = 0.75 CLVDD2fCK p1=0.5 p1=0.25 p0=0.75 p1=0.5 Copyright Agrawal, 2007 ELEC6270 Spring 09, Lecture 15

Charge Leakage Precharge CK Evaluate VDD Output A’ CK A=0 A’ CL Ideal Actual Time J. M. Rabaey, A. Chandrakasan and B. Nokolić, Digital Integrated Circuits, Upper Saddle River, New Jersey: Pearson Education, 2003. Copyright Agrawal, 2007 ELEC6270 Spring 09, Lecture 15

Bleeder Transistor VDD VDD CK A B C D CK A B C D Output Output CL CL Copyright Agrawal, 2007 ELEC6270 Spring 09, Lecture 15

A Problems With Dynamic CMOS VDD VDD CK A B C prech. evaluate CK A=0→1 CK B C J. M. Rabaey, A. Chandrakasan and B. Nokolić, Digital Integrated Circuits, Upper Saddle River, New Jersey: Pearson Education, 2003. Copyright Agrawal, 2007 ELEC6270 Spring 09, Lecture 15

Remedy Set all inputs to gates to 0 during precharge. Since precharge raises all outputs to 1, inserting inverters between gates will do the trick. Copyright Agrawal, 2007 ELEC6270 Spring 09, Lecture 15

Domino CMOS VDD VDD CK A B C prech. evaluate CK A=0→1 CK C B R. H. Krambeck, C. M. Lee and H.-F. S. Law, “High-Speed Compact Circuits with CMOS,” IEEE J. Solid-State Circuits, vol. SC-17, no. 3, pp. 614-619, June 1982. Copyright Agrawal, 2007 ELEC6270 Spring 09, Lecture 15

Bleeder in Domino CMOS VDD CK A Output B C CL D Copyright Agrawal, 2007 ELEC6270 Spring 09, Lecture 15

Logic Mapping for Noninverting Gates AND A B C D E F G H ABC X Y G+H AND/OR OR ABC D E F G+H Y Copyright Agrawal, 2007 ELEC6270 Spring 09, Lecture 15

Selecting a Logic Style Static CMOS: most reliable and predictable, reasonable in power and speed, voltage scaling and device sizing are well understood. Pass-transistor logic: beneficial for multiplexer and XOR dominated circuits like adders, etc. For large fanin gates, static CMOS is inefficient; a choice can be made between pseudo-nMOS, dynamic CMOS and domino CMOS. Copyright Agrawal, 2007 ELEC6270 Spring 09, Lecture 15