Introduction to VLSI Programming TU/e course 2IN30 Lecture 2: Control Handshake Circuits (1) Prof.dr.ir Kees van Berkel [Dr. Johan Lukkien] [Dr.ir. Ad Peeters]

Philips Research, Kees van Berkel, Ad Peeters, TU/e Time table 2005 dateclass | labsubject Aug. 302 | 0 hoursintro; VLSI Sep. 63 | 0 hourshandshake circuits Sep. 133 | 0 hourshandshake circuits assignment Sep. 203 | 0 hoursTangram Sep. 27no lecture Oct. 4 no lecture Oct. 111 | 2 hoursdemo, fifos, registers | deadline assignment Oct. 181 | 2 hoursdesign cases; Oct. 251 | 2 hoursDLX introduction Nov. 11 | 2 hourslow-cost DLX Nov. 81 | 2 hourshigh-speed DLX Nov. 29deadline final report

Philips Research, Kees van Berkel, Ad Peeters, TU/e Last Week – Lecture 1

Philips Research, Kees van Berkel, Ad Peeters, TU/e Transistors CMOS is the dominant IC technology today (Complementary Metal Oxide Semiconductor) Two types of transistors are used –PMOS and NMOS Dimensions of transistors are scaled by  2 in every new generation –0.5      - 90n - 70n - … This halves their area and makes them faster

Philips Research, Kees van Berkel, Ad Peeters, TU/e CMOS circuits Pull-up stack consisting of only P-mosts Pull-down stack consisting of only N-mosts Only inverting gates can thus be formed Vdd Vss + – V Pull-up Pull-down P N

Philips Research, Kees van Berkel, Ad Peeters, TU/e Boolean functions and transistors Transistors can be put in series –Conducting only if all conducting –This implements an AND function Transistors can be put in parallel –Conducting if either is conducting –This implements an OR function Networks can build AND/OR functions

Philips Research, Kees van Berkel, Ad Peeters, TU/e Production rules Production rules are guarded commands that specify (CMOS) gates –  F  z , G  z   Interpretation –do F then z:=true or G then z:=false od Guards must be mutually exclusive (environment) A gate is combinational if F  G is a tautology and it is sequential (state-holding) otherwise Guards must be stable: once a guard is true it must remain true until completion of transition

Philips Research, Kees van Berkel, Ad Peeters, TU/e Combinational CMOS gates Guards of production rules are complementary  F  z ,  F  z   This translates into z = F Combinational functions can be decomposed into inverting boolean functions These can be implemented directly in CMOS transistor stacks

Philips Research, Kees van Berkel, Ad Peeters, TU/e NAND gate z =  (a  b) Inverting function, hence single CMOS stage  a   b  z  –Two P-mosts in parallel a  b  z  –Two N-mosts in series Vss Vdd ab a b a b z z

Philips Research, Kees van Berkel, Ad Peeters, TU/e AND gate z = a  b – a  b  z  –  a   b  z  Non-inverting function, hence two CMOS stages First stage: NAND-gate –  a   b  y  – a  b  y  Second stage: Inverter –  y  z  – y  z  Vss Vdd ab a b a b z z y

Philips Research, Kees van Berkel, Ad Peeters, TU/e And-Or-Invert functions z =  (a  (b  c)) Inverting function, hence single CMOS stage  a  (  b   c)  z  –Three P-mosts a  ( b  c)  z  –Three N-mosts Vss Vdd a b a b z c c

Philips Research, Kees van Berkel, Ad Peeters, TU/e Exclusive-Nor in 10 transistors z = a  b = (a  b)  (  a   b) =  (a  b)   (a  b) =  (  (a  b)  (a  b)) y =  (a  b)Nand-gate, 4 mosts z =  (y  (a  b))Or-And-Inv-gate, 6 mosts

Philips Research, Kees van Berkel, Ad Peeters, TU/e Sequential CMOS gates Guards of production rules are not complementary  F  z , G  z   This translates into z = F  (z   G) –Or (equivalently)  z = G  (  z   F) This can be decomposed in two combinational functions y =  (F  (z   G)) and z =  y Combinational function F  (z   G) can be transformed into basic inverting functions

Philips Research, Kees van Berkel, Ad Peeters, TU/e Realization of a Muller-C element Production rules –  a  b  z ,  a   b  z  Implementation –z = F  (z   G ) –z = a  b  (z  (a  b )) –z = (a  b)  (b  z)  (z  a) –z = majority(a,b,z) Maj a b z C z a b

Philips Research, Kees van Berkel, Ad Peeters, TU/e Realization of a Muller-C element Vss Vdd a b a b z z a b z a b

Philips Research, Kees van Berkel, Ad Peeters, TU/e Realization of a Muller-C element Vss Vdd a b a b z z a b z a b

Philips Research, Kees van Berkel, Ad Peeters, TU/e Realization of an asymmetric C element Production rules –  a  b  z ,  b  z  Implementation –z = F  (z   G ) –z = (a  b)  (z  b) –z = b  (a  z) Or-And-Inv plus an inverter 8 transistors C z a b +

Philips Research, Kees van Berkel, Ad Peeters, TU/e VLSI basics Vdd (power) Vss (ground) C + – V Charge Q wire gate

Philips Research, Kees van Berkel, Ad Peeters, TU/e VLSI metrics dimensionless quantities (0.25  m CMOS): Aareagate equivalent (Nand, 4 mosts) (33  m 2, or 30,000 geq/mm 2 ) Ttimegate delay (0.35 nanosecond) (per basic inverting CMOS gate) Eenergytransition (1 picojoule) (per basic inverting CMOS stage)

Philips Research, Kees van Berkel, Ad Peeters, TU/e This Week – Lecture 2

Philips Research, Kees van Berkel, Ad Peeters, TU/e Handshake protocol Handshake between active and passive partner Communication is by means of alternating request (from active to passive) and acknowledge (from passive to active) signals Active: send request, then wait for acknowledge Passive: wait for request, then send acknowledge ActivePassive

Philips Research, Kees van Berkel, Ad Peeters, TU/e Handshake component: sequencer Sequencer Master Task 1 Task 2

Philips Research, Kees van Berkel, Ad Peeters, TU/e Four-phase handshake protocol Circuit level implementation has separate wires for request and acknowledge Four-phase handshake protocol implements return-to-zero of these wires Active Side Req := 1 ; Wait (Ack); Req := 0 ; Wait (-Ack); Passive Side Wait (Req); Ack := 1; Wait (-Req); Ack := 0; Req Ack

Philips Research, Kees van Berkel, Ad Peeters, TU/e Handshake signaling active sidepassive side request a r acknowledge a k request a r time event sequence: a r  a k  a r  a k 

Philips Research, Kees van Berkel, Ad Peeters, TU/e Handshake behaviors Let x i be boolean variables, and S i commands: skip always terminates without effect x  is a shorthand for x:= true and x  for x:= false S 1 ; S 2 denotes sequential execution of S 1 and S 2 S 1 || S 2 denotes parallel execution of S 1 and S 2 Program notation inspired by [Martin].

Philips Research, Kees van Berkel, Ad Peeters, TU/e Handshake behaviors Let G i be boolean expressions. Selection [G 1  S 1 [] … [] G N  S N ] execute an arbitrary S i for which guard G i holds. When no guard holds then suspend execution until otherwise. Repetition  [G 1  S 1 [] … [] G N  S N ] repeatedly execute S i for which G i holds until all guards are false.

Philips Research, Kees van Berkel, Ad Peeters, TU/e Useful shorthands ‘wait until’ [G] = [G  skip] Note: [G] ; S = [G  S] Unbounded repetition  [S] =  [true  S]

Philips Research, Kees van Berkel, Ad Peeters, TU/e Useful shorthands Four-phase handshakes –a  = [ar] ; ak  ; [  ar] ; ak  –a  = ar  ; [ak] ; ar  ; [  ak] Two-phase handshakes –a  = [ar] ; ak  –a  = [  ar] ; ak  –a   = ar  ; [ak] –a   = ar  ; [  ak]

Philips Research, Kees van Berkel, Ad Peeters, TU/e Reorder properties In the absence of timing assumptions, 1.One cannot observe the order of output transitions x1  ; x2  = x2  ; x1  = x1  || x2  2.One cannot fix the order of input transitions [x1] ; [x2] = [x2] ; [x1] = [x1] || [x2] = [x1  x2]

Philips Research, Kees van Berkel, Ad Peeters, TU/e Enclosure and properties Enclosure –a  : S = [ ar] ; S ; ak  –a  : S = [  ar] ; S ; ak  Reorder property a  : b  = [a r ] ; ([b r ] ; b k  ) ; a k  = [b r ] ; ([a r ] ; a k  ) ; b k  = b  : a 

Philips Research, Kees van Berkel, Ad Peeters, TU/e Decomposition rule Let program P = … S … and let a be a “fresh” channel Program P can be decomposed into two parallel processes: P’ = … a   ; a   … and  [a  : S ; a  ]

Philips Research, Kees van Berkel, Ad Peeters, TU/e Some handshake components Repeater : [a  :  [b   ; b   ] ] Mixer :  [ [ a  : c   ; [a  : c   ] [] b  : c   ; [b  : c   ] ] ] Sequencer :  [[a  : (b   ; b   ; c   ) ] ; [a  : c   ]]  a b a ; b c | a c b

Philips Research, Kees van Berkel, Ad Peeters, TU/e Handshake circuit: duplicator For each handshake on a 0  the duplicator produces two handshakes on a 1   [[a 0  : (a 1   ; a 1   ; a 1   ) ] ; [a 0  : a 1   ]] cf. Handshake behavior sequencer.

Philips Research, Kees van Berkel, Ad Peeters, TU/e Time for a break

Philips Research, Kees van Berkel, Ad Peeters, TU/e Production rules Production rules are guarded commands that specify (CMOS) gates –  F  z , G  z   Interpretation –do F then z:=true or G then z:=false od Guards must be mutually exclusive (environment) A gate is combinational if F  G is a tautology and it is sequential (state-holding) otherwise Guards must be stable: once a guard is true it must remain true until completion of transition

Philips Research, Kees van Berkel, Ad Peeters, TU/e Behavior of a gate network Gate network is the union of all pairs of production rules (gates) The concurrent execution of this set of PRs amounts to [Martin]:  [ select a PR ; fire that PR] If guard of PR equals false, firing = skip (firing a PR is an atomic action)

Philips Research, Kees van Berkel, Ad Peeters, TU/e Initializable A handshake component realization is initializable : when all inputs are false, the gate network must autonomously proceed to an initial state; when all passive inputs are false, the component must autonomously proceed to a state with all active outputs false.

Philips Research, Kees van Berkel, Ad Peeters, TU/e Handshake components: realization From handshake notation to gate network in 8 steps: 1 Specify component in handshake notation. 2 Expand to individual boolean variables (wires). 3 Introduce auxiliary state variables (if required). 4 Derive a set of production rules that implements this refined specification. 5 Make production rules more symmetric (cheaper). 6 (Verify isochronic forks.) 7 Verify initialization constraints. 8 Analyze time, area, and energy.

Philips Research, Kees van Berkel, Ad Peeters, TU/e Handshake components realizations Connector: trivial Repeater: alternative ‘symmetrizations’ Mixer: isochronic forks Sequencer: introduction of auxiliary variable Duplicator: up to you? Selector: up to you!

Philips Research, Kees van Berkel, Ad Peeters, TU/e Connector realization Behavior:  [a  : b   ; a  : b   ] Expansion:  [ [a r ] ; b r  ; [b k ] ; a k  ; [  a r ] ; b r  ; [  b k ] ; a k  ] Production rules: b k  a k  a r  b r   b k  a k   a r  b r  A pair of wires (!): no area, no delay, no energy. a b

Philips Research, Kees van Berkel, Ad Peeters, TU/e Repeater realization Behavior: [a  :  [b   ; b   ] ] Expansion: [ [a r ] ;  [ b r  ; [b k ] ; b r  ; [  b k ] ] ; a k  ] Production rules: false  a k  a r   b k  b r  true  a k  b k  b r  However, not initializable!  a b

Philips Research, Kees van Berkel, Ad Peeters, TU/e Repeater realizations

Philips Research, Kees van Berkel, Ad Peeters, TU/e Repeater: area, delay, energy Area: 2 gate equivalents Delay per cycle: 2 gate delays Energy per cycle: 2 transitions

Philips Research, Kees van Berkel, Ad Peeters, TU/e Mixer realization Behavior:  [ [ a  : c   ; a  : c   [] b  : c   ; b  : c   ] ] Restriction:  a r   b r must hold at all times! Expansion:  [ [ [a r ] ; c r  ; [c k ] ; a k  ; [  a r ] ; c r  ; [  c k ] ; a k  [] [b r ] ; c r  ; [c k ] ; b k  ; [  b r ] ; c r  ; [  c k ] ; b k  ] ] a c b |

Philips Research, Kees van Berkel, Ad Peeters, TU/e Mixer realization Production rules: a r  c k  a k  b r  c k  b k   c k  a k   c k  b k  a r  b r  c r   a r   b r  c r  More symmetric production rules: a r  c k  a k  a r  c k  a k   a r   c k  a k   a r   c k  a k  premature a k  more expensive | a c b

Philips Research, Kees van Berkel, Ad Peeters, TU/e Mixer realizations Mixer: area, delay, energy Area: 6 gate equivalents Delay per cycle: 8 gate delays Energy per cycle: 8 transitions

Philips Research, Kees van Berkel, Ad Peeters, TU/e Assignment: duplicator realization Behavior:  [[a  : (b   ; b   ; b   ) ] ; [a  : b   ]] Required:realization with 2 sequential gates (sequencer + mixer requires 3 sequential gates) Follow all 8 realization steps!! Add comparison with sequencer+mixer realization. #2 a b

Philips Research, Kees van Berkel, Ad Peeters, TU/e Duplicator chains Assume a M toggles at frequency f. Hence a 0 toggles at frequency f / 2 M. Let E dup be the duplication energy per cycle. Power of duplicator chain equals P = f E dup (1/2 + 1/4 + 1/8 +...) < f E dup

Philips Research, Kees van Berkel, Ad Peeters, TU/e For those who are interested in the details Synthesis of Asynchronous VLSI Circuits –Alain J. Martin –Caltech CS-TR –PostScript link via async.bib (html version) Programming in VLSI: From communicating processes to delay-insensitive circuits –Pages 1–64 in C.A.R. Hoare, ed., –Developments in Concurrency and Communication

Philips Research, Kees van Berkel, Ad Peeters, TU/e General asynchronous background Principles of Asynchronous Circuit Design –Eds. Jens Sparsø and Steve Furber –Kluwer Academic Press, Dec –ISBN The ‘Asynchronous’ Bibliography – The Asynchronous Logic Home Page –

Philips Research, Kees van Berkel, Ad Peeters, TU/e Next week: lecture 3 Outline: Handshake components … and their realization as networks of gates Handshake circuits Initialization of handshake circuits