1 B. Bruidegom Computer Architecture Top down approach B. Bruidegom AMSTEL-instituut

2 B. Bruidegom Basic Components Program Counter (PC) Instruction Memory Registers Arithmetic Logic Unit (ALU) Data Memory

3 B. Bruidegom Simplified View of a Harvard Architecture Instruction Memory Registers (16)Data Memory ALU PC Instruction Data Address Register # Data

4 B. Bruidegom 16 bit Data-path Instruction Memory Registers (16)Data Memory ALU PC Instruction Data Address Register # Data

5 B. Bruidegom Simplified View of a Harvard Architecture Instruction Memory RegistersData Memory ALU PC Instruction Data Address Register # Data Two types of functional units: elements that operate on data values (combinational) elements that contain state (sequential )

6 B. Bruidegom Simplified View of a Harvard Architecture Instruction Memory RegistersData Memory ALU PC Instruction Data Address Register # Data Two types of functional units: elements that operate on data values (combinational) elements that contain state (sequential )

7 B. Bruidegom Simplified View of a Harvard Architecture Instruction Memory RegistersData Memory ALU PC Instruction Data Address Register # Data Two types of functional units: elements that operate on data values (combinational) elements that contain state (sequential ) Edge triggered Level Triggered CLOCK Edge

8 B. Bruidegom Voorbeeld van een instructie: ADD Instruction Memory RegistersData Memory ALU PC Instruction Data Address 1 st register # 2 nd register # Dest. reg. # Data ADD $r0, $r1, $r2 $r0 = $r1 + $r2 Assembly Language

9 B. Bruidegom Voorbeeld van een immediate instructie: ADDI Instruction Memory RegistersData Memory ALU PC Instruction Data Address 1 st register # 2 nd register # Dest. reg. # Data ADDI $r0, $r1, 100 $r0 = $r

10 B. Bruidegom De load-instructie LW: Register  Memory Instruction Memory RegistersData Memory ALU PC Instruction Data Address 1 st register # 2 nd register # Dest. reg. # Data LW $r0, 100($r1) $r0 = Memory[$r ] 100

11 B. Bruidegom Branch-instruction: Branch Equal BEQ Instruction Memory RegistersData Memory ALU PC Instruction Data Address 1 st register # 2 nd register # Dest. reg. # Data BEQ $r0, $r1, 100 IF($r0 == $r1) GOTO z

12 B. Bruidegom Vijf fases van een instructie Instruction Memory Registers (16)Data Memory ALU PC Instruction Data in Address 1 st register # 2d register # Dest. reg. # Data in 1: Instruction fetch2: Instruction decode3: Execution 5: Write back Figuur 10 Vijf fases van een instructie Data out 4: Memory access

13 B. Bruidegom Welke instructie gebruikt welke fase? Instruction type Instruction fetch Instruction decode ExecuteMemory access Write back LIx xx ADDx xxx ADDI LW SW BEQ

14 B. Bruidegom 16 bit Harvard Processor

15 B. Bruidegom Voorbeeld van een immediate instructie: Load Immediate Instruction Memory RegistersData Memory ALU PC Instruction Data Address 1 st register # 2 nd register # Dest. reg. # Data LI $r1, 0x1FD $r1 = 0x1FD 1FD

16 B. Bruidegom 16 bit Harvard Processor LI $1, 0x1FD

17 B. Bruidegom 16 bit Harvard Processor LI $1, 0x1FD

18 B. Bruidegom 16 bit Harvard Processor LI $1, 0x1FD

19 B. Bruidegom 16 bit Harvard Processor LI $1, 0x1FD

20 B. Bruidegom ALU tabel ALU 2 ALU 1 ALU 0 operatie 000complement van B 001BB wordt doorgegeven 010A - Brekenkundige - 011A plus Brekenkundige A  B bitwise XOR 101A + Bbitwise OR 110A. Bbitwise AND

21 B. Bruidegom Instruction format

22 B. Bruidegom Instruction format Mem Write Mem ToReg Br2Re g Reg Writ e ALUOpcod e OpA rs OpB rt Dest rd Immediate nr of bit s NOT x180rtrd0 MOVE x190rtrd0 LDI x0900rdimmediate ADD x1Brsrtrd0 SUB ADDI ANDI BEQ LW SW

23 B. Bruidegom Instruction set 16 bit Harvard machine MnemonicMeaning ExampleMeaning MOVE rd, rtCopy register MOVE $1, $2 r1  r2 NOT rd, rtOne complement NOT $1, $2 r1  ~r2 SUB rd, rs, rtSubtract SUB $4, $2, $3 r4  r2 - r3 ADD rd, rs, rtAdd ADD $4, $2, $3 r4  r2 + r3 XOR rd, rs, rtBitwise exclusive or XOR $4, $2, $3 r4  r2  r3 OR rd, rs, rtBitwise or ADD $4, $2, $3 r4  r2 | r3 AND rd, rs, rtBitwise and ADD $4, $2, $3 r4  r2 & r3 LI rd, immLoad Immediate LDI $1, 0x34 r1  0x34 NOTI rd, imm Not ImmediateNOTI $1, 0x34 r1  ~0x34 SUBI rd, rs, immSub Immediate SUBI $1, $2, 0x34 r1  r2 - 0x34 ADDI rd, rs, immAdd Immediate ADDI $1, $2, 0x34 r1  r2 + 0x34 XORI rd, rs, immXOR Immediate XORI $1, $2, 0x34 r1  r2  0x34 ORI rd, rs, immOr Immediate ADDI $1, $2, 0x34 r1  r2 | 0x34 ANDI rd, rs, immAnd Immediate ADDI $1, $2, 0x34 r1  r2 & 0x34 BRA offsetBranch Always to “label” BRA label PC  PC + offset BZ rt, offsetBranch if rt = 0 BZ $6, endIf (r6 = 0) goto ‘end’ BEQ rs, rt, offsetBranch if rs = rt BEQ $6, $8, loopIf (r6 = r8) goto ‘loop’ LW rd, rs,indexLoad Word from Memory LW $2, 0x8($1) R2  Address (8 + r1) SW rs, rt, indexStore Word to Memory SW $2, 0x8($1) Address (8 + r1)  r2