Reliability Enhancement via Sleep Transistors Frank Sill Torres +, Claas Cornelius*, Dirk Timmermann* + Department of Electronic Engineering, Federal University of Minas Gerais, Belo Horizonte, Brazil *Inst. of Applied Microelectronics and Computer Engineering, University of Rostock, Germany

2 Sill Torres et al.– Reliability w/ Sleep Transistors Focus / Main ideas 1.Approach for extension of expected lifetime 2.Application of simulation environment for MTTF estimation

3 Sill Torres et al.– Reliability w/ Sleep Transistors  Motivation  Preliminaries  Reliability Enhancement via Sleep Transistors  Simulation Environment  Results  Conclusion Outline

4 Sill Torres et al.– Reliability w/ Sleep Transistors Probability for failures increases due to:  Increasing transistor count  Shrinking technology Motivation Technology Development Wolfdale 410 Mil. Northwood 55 Mil. Prescott 125 Mil. Yonah 151 Mil. Gulftown Mil. Wolfdale 410 Mil. Tecnology

5 Sill Torres et al.– Reliability w/ Sleep Transistors Motivation Error classification Error PermanentTemporary Soft errors, Voltage drop, Coupling, … Reduced Performance Process variations, Electro- migration, Oxide wearout, NBTI,... Malfunction Electromigration, Oxide breakdown...

6 Sill Torres et al.– Reliability w/ Sleep Transistors Preliminaries  Very well-known and effective approach for leakage reduction  Insertion of sleep transistors (mostly with high-threshold voltage) between logic module and supply  Disconnection from supply during standby Power-Gating with Sleep Transistors M. Powell, et al., Proc. ISLPED, A. Ramalingam, et al., Proc. ASP-DAC, Sleep virtual GND Logic block virtual VDD High-V th

7 Sill Torres et al.– Reliability w/ Sleep Transistors  Electromigration (EM) –Performance reduction and errors –Depending on currents and temperature  Negative Bias Temperature Instability (NBTI) –Performance reduction –Depending on voltage level and temperature  Time Dependent Dielectric Breakdown (TDDB) –Performance reduction and errors –Depending on voltage level and temperature Preliminaries Time Dependent Failure Mechanisms Increase of lifetime through reduction of supply voltage and activity

8 Sill Torres et al.– Reliability w/ Sleep Transistors SLEEP  Basic idea: Reduction of degradation via module deactivation  Problem: What to do at run-time? Reliability Enhancement via Sleep Transistors Concept and Realization Module Module 1 Instance 2 Module 1 Instance 2 Module 1 Instance 1 Module 1 Instance 1 Module 2 MUX t life-new ≈ t life-old + t off t life-system = t life-module ≈ t life-old + t off ≈ 2* t life-old + t sleep

9 Sill Torres et al.– Reliability w/ Sleep Transistors  Lifetime –Increase by more than factor 2 (not linear relation between effective voltage and failure mechanisms)  Area –Increase by slightly more than factor 2 –Ca. 50 % less than Triple Modular Redundancy (TMR)  Power dissipation –Slight increase of dynamic power dissipation –Increase of leakage by ca. factor 2  Delay –Slight increase through multiplexer delays Reliability Enhancement via Sleep Transistors Expectations

10 Sill Torres et al.– Reliability w/ Sleep Transistors  Application –Limited improvements for devices with long standby times (mobiles, home PCs) –High improvements for high availability applications (server, aerospace equipment, mobile communication nodes)  Multiplexer –Problem: no deactivation of multiplexer –Solution: use of transmission gates (less vulnerable)  Control signals (for sleep transistor, multiplexer) –Logic for control signal generation must be reliable too –Hence: reliable implementation (HighTox, wire widening, …) –More research required Reliability Enhancement via Sleep Transistors Comments

11 Sill Torres et al.– Reliability w/ Sleep Transistors  Desired: Simulative estimation of average time until first failure (also known as Mean Time To Failure – MTTF)  Solution: –Application of voltage controlled variable elements and parameters for failure modeling (xSpice, VerilogA, …) –Linear increase/decrease of control voltage at simulation time  Example: HSPICE model of transistor with TDDB and varying width Simulation Environment V0 Vref 0 DC 1 V1 Vctrl 0 PULSE 1e E-2 1E-9 1E1 2E1 M0 D G N1 0 nmos W='1e-7 * V(Vctrl)/V(Vref)' M1 N1 G S 0 nmos W='1e-7 * V(Vctrl)/V(Vref)' G1 G N1 VCR Vctrl 0 10

12 Sill Torres et al.– Reliability w/ Sleep Transistors Results Mean Time To Failure (MTTF) (BPTM 22nm, 100 samples, TDDB and EM modeling, basic MTTF of 300 clock cycles, relaxed timing, w/o temperature consideration) 2.2

13 Sill Torres et al.– Reliability w/ Sleep Transistors Results Delay / Power / Area Average values: Delay: + 7 %, Power: + 5 %, Area: %

14 Sill Torres et al.– Reliability w/ Sleep Transistors Conclusion  Progressing susceptibility of current technologies against severe failure mechanisms  Extension of expected lifetime by alternating (de-)activation of redundant blocks via sleep transistors  Environment for simulation of time-dependent degradation of design components  Increase of MTTF by more than factor 2 through proposed approach  Factor 1.2 for relation of average increase of MTTF and area  Future tasks: –Application of selective redundancy techniques –Merging with approaches on system level –Analysis of control logic

15 Sill Torres et al.– Reliability w/ Sleep Transistors Thank you!

16 Sill Torres et al.– Reliability w/ Sleep Transistors Motivation Time-Dependent Dielectric Breakdown (TDDB)  Tunneling currents Wear out of gate oxide  Creation of conducting path between Gate and Substrate, Drain, Source  Depending on electrical field over gate oxide, temperature (exp.), and gate oxide thickness (exp.)  Also: abrupt damage due to extreme overvoltage (e.g. Electro- Static Discharge) Source: Pey&Tung

17 Sill Torres et al.– Reliability w/ Sleep Transistors Reliability Enhancement via Sleep Transistors Realization

18 Sill Torres et al.– Reliability w/ Sleep Transistors Reliability Enhancement via Sleep Transistors Blocks / Requirements

19 Sill Torres et al.– Reliability w/ Sleep Transistors Simulation Environment Overview

20 Sill Torres et al.– Reliability w/ Sleep Transistors Simulation Environment Error Modeling