April 28th, 2011Timing Workshop, Chicago Paul Scherrer Institute Limiting factors in Switched Capacitor Arrays Sampling speed, Timing accuracy, Readout speed Stefan Ritt

Follow-up: Optimal Sampling Speed April 28th, 2011Timing Workshop, Chicago Threshold Theory (Nyquist): 1 GHz signal: 350 ps rise-time, 2 GSPS Reality: Noise! (e.g. quantization noise of ADC) and tail of input power 350 ps 500 ps

Stefan Ritt Measured Resol. Mod724, 14 bit, 100 MS/s April 28th, 2011Timing Workshop, Chicago 50 mV 100 mV 200 mV 500 mV StdDev (ns) 5*T C. Tintori

Stefan RittMarch 15th, 2011DPP Workshop PSI Switched Capacitor Array Shift Register Clock IN Out “Time stretcher” GHz  MHz Waveform stored Inverter “Domino” ring chain ns FADC 33 MHz

Stefan RittApril 28th, 2011Timing Workshop, Chicago Limits on sampling speed vs. technology

Stefan Ritt Inverter chain April 28th, 2011Timing Workshop, Chicago RC-delay with TG Starved inverters Layout more compact Used in DRS4 chip TG in signal path Parasitics of TG counts Layout more compact Used in DRS4 chip TG in signal path Parasitics of TG counts Used in most designs “Starving” trans. outside signal path Parasitics do not count Used in most designs “Starving” trans. outside signal path Parasitics do not count

Stefan Ritt C par = 5 fFTransmission Gates Starved Inverters 0.25 UMC3.7 GHz13.0 GHz 0.25 UMC GAA5.9 GHz 0.13 IBM2.1 GHz17.9 GHz 0.11 UMC3.8 GHz20.3 GHz 0.11 UMC HS4.1 GHz23.0 GHz Achievable sampling speeds April 28th, 2011Timing Workshop, Chicago Starved inverters better than TG Speed does not linearly scale with technology (parasitics limited) High speed (low V t ) option helps Starved inverters better than TG Speed does not linearly scale with technology (parasitics limited) High speed (low V t ) option helps DRS4

Stefan Ritt Today highest sampling speed April 28th, 2011Timing Workshop, Chicago 130 IBM, J.-F. Genat, Clermont-Ferrand, Jan. 2011

Stefan Ritt Interleaved sampling April 28th, 2011Timing Workshop, Chicago Fine tuning delays STURM chip (Gary): O(100 GSPS) For fixed interleaving, this can also be achieved by chip layout Alternative: Comparators with different thresholds Fine tuning delays STURM chip (Gary): O(100 GSPS) For fixed interleaving, this can also be achieved by chip layout Alternative: Comparators with different thresholds

Stefan RittApril 28th, 2011Timing Workshop, Chicago Limits on analog bandwidth Parasitics, bond wires, R on of sampling cell

Stefan Ritt PCB April 28th, 2011Timing Workshop, Chicago Detector (covered in next talks) Connector (LEMO connector has a BW of ∼ 500 MHz) Cable (RG58: 5 m has a -3db BW of 1 GHz) PCB Preamplifier Chip package On-chip bus Analog cell switch Storage capacitor Signal Chain Det. Chip C par

Stefan RittApril 28th, 2011Timing Workshop, Chicago Influence on chip package Bond wire has ~2-3 nH and thus limits the BW to 2-3 GHz Input inductance can be reduced by using bump bonding or stud bonding 200  m 75  m Wire Bump Stud

Stefan Ritt Effect of “write bus” April 28th, 2011Timing Workshop, Chicago DRS3: 300 MHz with 2  m width Length: 3500 u Widths: 4x8u, 4x14u (beginning/end of bus)

Stefan Ritt Influence on parasitics April 28th, 2011Timing Workshop, Chicago DRS3: 300 MHz with 2u width Minimal write switch has ~10 fF parasitic capacitance Write bus has resistance of ~0.05 Ohm/square (0.013 Ohm square for 20k top metal option) → 15 Ohm after 3 mm bus + bond wire (1.5 Ohm) → 10 pF after 3 mm Minimal write switch has ~10 fF parasitic capacitance Write bus has resistance of ~0.05 Ohm/square (0.013 Ohm square for 20k top metal option) → 15 Ohm after 3 mm bus + bond wire (1.5 Ohm) → 10 pF after 3 mm DRS4

Stefan Ritt Write switch has a finite “on” resistance Storage cap needs to be >10 fF for reasonable kTC noise Leakage current requires even bigger C Simulation C store = 50 fF UMC 0.25 um technology V dd = 2.5V Minimal l W = 0.25 um * N Note: N>1 adds parasitic to write bus! Influence of write switch April 28th, 2011Timing Workshop, Chicago w opt. ~ 6 um -3db Bandwidth [GHz]

Stefan Ritt Smaller C store leads to higher bandwidth But: kTC noise → 20 fF for 11 bits Practical limit: ∼ 5 fF Important: Leakage current! Worse with smaller technologies Non-Gaussian distribution on chip Worse for low R on switch Temperature dependent Effect on sampling capacitor April 28th, 2011Timing Workshop, Chicago G. Varner

Stefan Ritt Leakage current April 28th, 2011Timing Workshop, Chicago Leakage current: Must be small to get  V<<1mV during readout Distribution has long tail Either make C large or keep storage time short Leakage current: Must be small to get  V<<1mV during readout Distribution has long tail Either make C large or keep storage time short G. Varner, 2010, Krakov

Stefan Ritt Comparison between technologies April 28th, 2011Timing Workshop, Chicago UMC k  6  m opt. 16 GHz UMC k  6  m opt. 16 GHz UMC k  180  m opt. 21 GHz UMC k  180  m opt. 21 GHz UMC 0.11 low V t 4 k  120  m opt. 37 GHz UMC 0.11 low V t 4 k  120  m opt. 37 GHz R on [k  ] V DS [V] dI/dU N/1000 BW [GHz]

Stefan RittApril 28th, 2011Timing Workshop, Chicago Bandwidth DRS4 (1024 sampling cells) Bandwidth is determined by bond wire and internal bus resistance/capacitance: 850 MHz (QFP), 950 MHz (QFN), ??? (flip-chip) 850 MHz (-3dB) QFP package final bus width Simulation Measurement

Stefan Ritt Bandwidth STURM2 (32 sampling cells) April 28th, 2011Timing Workshop, Chicago G. Varner, Dec. 2009

Stefan Ritt Optimal Chip Layout April 28th, 2011Timing Workshop, Chicago Bond Pad 32 sampling cells write+ write- …

Stefan RittApril 28th, 2011Timing Workshop, Chicago Limits on timing resolution Matching – PLL phase jitter – Aperture

Stefan Ritt “Matching” (inverter-to-inverter variation by statistical limits in doping) is fixed over time and can be corrected PLL phase jitter is typical 25 ps can can be corrected for with separate timing channel (DRS4: 8+1 channels) Residual cell jitter caused by V dd noise, short delay line is better Typical SCA PLL April 28th, 2011Timing Workshop, Chicago T Q Phase Comparator External Reference Clock Inverter Chain loop filter down 11 22 sampling speed control PLL up

Stefan RittApril 28th, 2011Timing Workshop, Chicago Residual aperture jitter Noise Timing V dd (GND) noise causes jitter Effect worse if rise time is slow (starving) Typical values: 100 ps rise time for 1.2 V signal 5 mV noise 32 cells Jitter: 5 mV/1.2 V * 100 ps * 32 = 13 ps Noise can originate off-chip (e.g. running ADC) Solution: Differential inverters, LDO on chip Disadvantage: More power V dd (GND) noise causes jitter Effect worse if rise time is slow (starving) Typical values: 100 ps rise time for 1.2 V signal 5 mV noise 32 cells Jitter: 5 mV/1.2 V * 100 ps * 32 = 13 ps Noise can originate off-chip (e.g. running ADC) Solution: Differential inverters, LDO on chip Disadvantage: More power

Stefan RittApril 28th, 2011Timing Workshop, Chicago Limits on readout speed Analog-Digital readout, multi-buffer

Stefan Ritt Readout time April 28th, 2011Timing Workshop, Chicago N input channels M output channels t readout = N/M * n samples * t sample Analog: t sample = 20 – 100 ns (external ADC MHz) Digital: t sample = 5 – 10 ns * n bits / n lines 1024 samples, 10 bits, N=8, M=1 → t readout = 400  s 32 samples, 10 bits, N=8, M=8 → t readout = 1.6  s Analog: t sample = 20 – 100 ns (external ADC MHz) Digital: t sample = 5 – 10 ns * n bits / n lines 1024 samples, 10 bits, N=8, M=1 → t readout = 400  s 32 samples, 10 bits, N=8, M=8 → t readout = 1.6  s

Stefan RittMarch 25th, 2011FEE2010, Bergamo ROI readout mode in DRS4 readout shift register Trigger stop normal trigger stop after latency Delay delayed trigger stop Patent pending! 33 MHz

Stefan Ritt “Multi-buffering” can reduce dead time for Poisson-distributed events Multi buffering April 28th, 2011Timing Workshop, Chicago Event is stored in first buffer Event occurring during readout of first event is stored in second buffer R: event rate [Hz] T: readout time [s] LT: “live time” N: Number of buffers R: event rate [Hz] T: readout time [s] LT: “live time” N: Number of buffers NLT 167 % 294 % % % R = 1 kHz, T=400  s Cumulative distribution function for Poisson-distributed events:

Stefan Ritt Has to accommodate trigger delay High energy physics experiments require 100’s of buffered events CMS: Possible hit every bunch crossing at 25 ns, 155 bunch crossings before L1 trigger ILC: ∼ 3000 bunch trains ∼ 5 Hz TOF-PET: > MHz event rate Storage Depth April 28th, 2011Timing Workshop, Chicago CTA ILC → Deep storage depth → Many storage segments → High event rate → Deep storage depth → Many storage segments → High event rate

Stefan Ritt The vision for the future April 28th, 2011Timing Workshop, Chicago The Perfect Chip Low number of input cells Deep Sampling Depth Deep Sampling Depth High event rate High event rate High event rate High event rate High channel density Low power Many analog buffers

Stefan RittMarch 15th, 2011DPP Workshop PSI Cascaded Switched Capacitor Arrays shift register input fast sampling stage secondary sampling stage fast sampling cells at 10 GSPS 100 ps sample time, 3.1 ns hold time Hold time long enough to transfer voltage to secondary sampling stage with moderately fast buffer (300 MHz) Shift register gets clocked by inverter chain from fast sampling stage 32 fast sampling cells at 10 GSPS 100 ps sample time, 3.1 ns hold time Hold time long enough to transfer voltage to secondary sampling stage with moderately fast buffer (300 MHz) Shift register gets clocked by inverter chain from fast sampling stage

Stefan RittMarch 15th, 2011DPP Workshop PSI Typical Waveform Only short segments of waveform are of interest

Stefan RittMarch 15th, 2011DPP Workshop PSI Dead-time free acquisition Self-trigger writing of 128 short 32-bin segments (4096 bins total) Simultaneous writing and reading of segments Quasi dead time-free Data driven readout Ext. ADC runs continuously ASIC tells FPGA when there is new data Possibility to skip segments → analog buffer for HEP experiments Coarse timing from 300 MHz counter Fine timing by waveform digitizing and analysis in FPGA 20 * 20 ns = 0.4  s readout time  2 MHz sustained event rate (ToF-PET) Attractive replacement for CFD+TDC DRS5 planned for 2013

Stefan Ritt SCAs will more and more replace Q-ADC and CFG+TDCs New designs are in the pipeline for >3 GHz analog BW, multi-buffering and fast readout Current limitations are are well known and will be pushed further in next generation of chips Conclusions April 28th, 2011Timing Workshop, Chicago