MULTIPROCESSOR OPERATING SYSTEM MODULE 8

PRESENTORS: JAMES REYES RYANNE NERY P. BACUD

MOTIVATIONS FOR MULTIPROCESSOR SYSTEMS Enhanced Performance. Multiprocessor systems increase system performance Fault Tolerance. A multiprocessor system exhibits graceful performance degradation to processor failures because of the availability of multiple processors.

BASIC MULTIPROCESSOR SYSTEM ARCHITECTURES According to the classification of Flynn, in MIMD (multiple instruction multiple data) architectures, multiple instruction streams operate on different data streams. In the broadest sense, an MIMD architecture qualifies as a full-fledged multiprocessor system. Thus, a multiprocessor system consists of multiple processors, which execute different programs (or different segments of a program) concurrently. The main memory is typically shared by all the processors. Based on whether a memory location can be directly accessed by a processor or not, there are two type s of multiprocessor system

Two types of multiprocessor systems: Tightly coupled Loosely coupled (Based on whether a memory location can be directly accessed by a processor or not, ) NEXT>>

Tightly Coupled In tightly coupled systems, all processors share the same memory address space and all processors can directly access a global main memory. Examples of commercially available tightly coupled systems are Multimax of Encore Corporation, Flex/32 of Flexible Corporation, and FX of Sequent Computers. Tightly coupled systems can use the main memory for interprocessor communication and synchronization. <<BACK

Loosely Coupled Systems In loosely coupled systems, not only is the main memory partitioned and attached to processors, but each processor has its own address space. Therefore, a processor cannot directly access the memory attached to other processors. One example of a loosely coupled systems is Intel’s Hypercube. Loosely coupled systems, on the other hand, use only message passing for interprocessor communication and synchronization. <<BACK

TYPES OF MULTIPROCESSOR SYSTEM UMA (uniform memory access) NUMA (nonuniform memory access) NORMA (no remote memory access) (Based on the vicinity and accessibility of the main memory to the processors) NEXT>>

UMA architectures The main memory is located at a central location such that it is equidistant from all the processors in terms of access (in the absence of conflicts). That is, all the processors have the same access time to the main memory. In addition to this centralized shared memory, processors may also have private memories, where they can cache data for higher performance. Some examples of UMA architectures are Multimax of Encore Corporation, Balance of Sequent, and VAX 8800 of Digital Equipment. <<BACK

NUMA architectures The main memory is physically partitioned and the partitions are attached to the processors. All the processors, however, share the same memory address space. A processor can directly access the memory attached to any other processor, but the time to access its own memory partition. Examples of NUMA architectures are cm* of CMU and Butterfly machine of BBN Laboratories. <<BACK

NORMA Architectures The main memory is physically partitioned and the partitions are attached to the processors. However, a processor cannot directly access the memory of any other processor. The processors must send message over the interconnection network to exchange information. An example of NORMA architecture is Intel’s Hypercube. <<BACK

INTERCONNECTING NETWORKS FOR MULTIPROCESSOR SYSTEMS The interconnection network in multiprocessor systems provides data transfer facility between processors and memory modules for memory access. The design of the interconnection network is the most crucial hardware issue in the design of multiprocessor systems. Generally, circuit switching is issued to establish a connection between processors and memory modules. Thus, during a data transfer, a dedicated path exists between the processor and the memory module. NEXT>>

Various types of interconnection networks include: Bus Cross-bar Switch Multistage Interconnection Network NEXT>>

Bus Processors are connected to memory modules via a bus. <<BACK

Cross-bar Switch A cross bar switch is a matrix (or grid structure) that has a switch at every cross-point. A cross-bar is capable of providing an exclusive connection between any processor-memory pair. <<BACK

Multistage Interconnection Network A multistage interconnection network is a compromise between a bus and a cross-bar switch. A multistage interconnection network permits simultaneous connection between several processor-memory pairs and is more cost-effective than a cross-bar. <<BACK

CACHING Multiprocessor systems commonly use caching to reduce memory access time. Under caching, every processor has a private memory, called cache, in addition to the shared global memory. When a processor needs to fetch a word from a data block in the global memory, it fetches the entire block and saves it in its cache for future use. ADVANTAGE DISADVAN TAGE <<NEXT

Caching has two other advantages First, the traffic over the interconnection network is reduced (because most memory accesses can be satisfied by the cache). Second contention at memory modules is reduced (because different blocks of a memory module can be fetched by several processors and can be accessed concurrently from their respective caches). <<BACK

The Cache Coherence Problem Caching poses s problem when a processor modifies a cached block that is also cached by some other processors currently. Modifying a cached block by a processor invalidates the copies of this block in the cache of other processors because these copies have an outdated value. This is called the cache coherence problem in multiprocessor system. <<BACK

HYPERCUBE ARCHITECTURES Hypercube based architectures have recently emerged as a viable alternative in the design of multiprocessor systems with a large number of processors. In an n-dimensional cube, where each node is connected to n other nodes. In hypercube based architectures, the processors are the nodes of a hypercube and a hypercube edge corresponds to a bi-directional communication link between two processors. Each of the 2n nodes of an n-cube are assigned a unique n-bit address ranging from 0 to 2n – 1 such that the addresses assigned to two adjacent nodes differ only in 1 bit position. The address of a node in the ith dimension of a node differs from that node’s address only in ith bit. The maximum distance between any two nodes in an n-cube is n hops. Thus, the delay characteristics of hypercube architectures grow logarithmically with the number of nodes and these architecture are highly scalable.