Cambridge University Engineering Department VLSI Design Third Year Standard Project - SB1 Second Mini Lecture Web page: 12th May - 6th June 2009 David M Holburn David Chuah Jiming Jiang

Cambridge University Engineering Department Summary of progress so far l Developed ring oscillator (RO) concept l Confirmed using VHDL & ModelSim l Explored effect of varying NOR delays ( ModelSim ) l Built symbol & schematic l Incorporated RO in Frequency Synthesiser design l Used Eldo to predict timing characteristics of RO using AMS NOR2 design l Investigated characteristics of real RO design using oscilloscope/counter

Cambridge University Engineering Department Labs 5 & 6 Lab Guide 5 l Gain familiarity with layout and IC Station layout editor l Adapt mask layouts for the 2-input NOR gate nor2x l Identify/correct design rule violations in nor2 layout Lab Guide 6 l Verification - check for proper correspondence between your nor2x layout & the nor2x transistor schematic l Check transistor dimensions W & L l Investigate effect of parasitic elements C and R in layout l Simulate the gate’s characteristics with parasitics using Eldo

Cambridge University Engineering Department The fabricated ring oscillator

Cambridge University Engineering Department Layout and stick diagrams p and n-type MOSFET channels MOSFET channels and interconnect Interconnect, channels and gate electrodes

Cambridge University Engineering Department Layout and stick diagrams (2) Output Contact cuts (one of four) Input

Cambridge University Engineering Department Form Factor Channels aligned horizontally Short, wide form factor Channels aligned vertically Tall, thin form factor Identical logic functions

Cambridge University Engineering Department Stick diagrams: NAND Output Input B Input A VDD VSS D S D S

Cambridge University Engineering Department Output in polySi crosses under VDD Stick diagrams: NOR Output wired in metal 1 Input B Input A VDD VSS NB: contact cut links m1 and poly

Cambridge University Engineering Department Design rules Mask : Poly1 4A Minimum poly1 width 0.35  m Current density must not exceed 500  A/  m 4C Minimum Poly1 spacing or notch width 0.45  m 4D Minimum Poly1 to Diffusion spacing 0.20  m 4B Minimum Gate length(0.35  m) 4E Minimum Poly1 extension on field oxide 0.40  m 4F Minimum source and drain width 0.50  m

Cambridge University Engineering Department Lab Guide 5 - layout of nor2x –add gate electrodes l IC Station operations –familiarise with basic techniques –study & understand layout –detect & correct rule violations –connect output –consider how to optimise layout »size »speed »convenience of input/output »compatible with other cells –plot completed layout

Cambridge University Engineering Department Eldo - for detailed simulation

Cambridge University Engineering Department DC characteristic for nor2x

Cambridge University Engineering Department Transient performance of nor2x

Cambridge University Engineering Department Parasitic capacitances in nor2t

Cambridge University Engineering Department Capacitances due to interconnect

Cambridge University Engineering Department Wiring parasitics

Cambridge University Engineering Department Response with all parasitics

Cambridge University Engineering Department Final week – Complete System Lab Guide 7 l Use Design Architect-IC to create top-level schematic l Incorporates all design blocks –Programmable divider and its sub-blocks –Ring Oscillator –Single NOR gate –Input/Output and Power pads l Simulate entire system using Eldo l May take several minutes to run!

Cambridge University Engineering Department Final week - Semi Custom Design Lab Guide 8 l Use IC Station, ICassemble & ICBlocks l Create complete IC layout for synthesiser module –Automatic and interactive floor-planning –Automatic cell placement –Automatic routing of interconnect –Flattened and Hierarchical designs l Generate colour check plot of result l Your design is complete!

Cambridge University Engineering Department Hierarchical layout design l Hierarchy - a methodology for creating larger design from smaller design objects l At lowest level objects are polygons, shapes and paths (leaf cells), e.g. nor2, nand2 l Inserted in a multi-tiered, hierarchical design l Designer controls visibility of detail l Allows construction of libraries of commonly used parts e.g. divider (based on count4) l Permits re-use of designs in other projects

Cambridge University Engineering Department Hierarchical Objects ring_oscillator control divider comparator single_nor

Cambridge University Engineering Department Example schematic for counter

Cambridge University Engineering Department Floor plan for counter

Cambridge University Engineering Department Place & Route standard cells All nets shown yellow are routed right away - unrouted nets in green

Cambridge University Engineering Department Example ring_oscillator schematic

Cambridge University Engineering Department Floorplan for ring_oscillator

Cambridge University Engineering Department Place & Route for ring_oscillator

Cambridge University Engineering Department Layout for Core (all blocks)

Cambridge University Engineering Department Top-level layout with I/O & power

Cambridge University Engineering Department Completed layout

Cambridge University Engineering Department Completed layout

Cambridge University Engineering Department The End

Cambridge University Engineering Department After compaction

Cambridge University Engineering Department Flattened layout top_level_flat