VLSI Testing 304-649 Jean-François Boland Design error and fault simulation.

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Presentation transcript:

VLSI Testing Jean-François Boland Design error and fault simulation

Presentation Plan Project Overview Design error and fault models ESIM Software Future work

Project Overview Simulation – Design error – Logical fault ESIM software, [Al-Asaad 00], [Hayes 00] – Fault and design errors models – Algorithms use for faults/errors simulation – Experimental results and performances

Error models Gate Substitution Errors (SIGSE, MIGSE) – 67% of all manual design errors Gate Count Errors (EGE, MGE) Input Count Errors (EIE, MIE) Wrong Input Errors (WIEs) Single Stuck-Line (SSL) Input Pattern (IP) Design error Fault error

Examples of design errors

ESIM Software Written using C++ (open source) Simulation algorithms for GP1 and GP2 errors Uses the netlist format of the ISCAS-85 benchmark circuits. Specifications Application Evaluate the coverage of design errors and logical faults of typical ATPG.

Future work GP1 and GP2 algorithms overview. Performances and experimental results analysis. ESIM functionality requirements. Limits and improvements.