doc.: IEEE f Submission March 2011 Paul Gorday, Sunrise Micro DevicesSlide 1 Project: IEEE P Working Group for Wireless Personal Area Networks (WPANs) Submission Title: [TG4f FM Deviation Tolerance] Date Submitted: [12 March, 2011] Source: [Paul Gorday, Fred Martin] Company [Sunrise Micro Devices] Address [9181 Glades Road, Suite 125, Boca Raton, Florida, USA] Voice:[ ], Re: [ f comment resolution] Abstract:[ Proposed FM deviation tolerance for f 433 MHz PHY] Purpose:[To be considered during f standard development process.] Notice:This document has been prepared to assist the IEEE P It is offered as a basis for discussion and is not binding on the contributing individual(s) or organization(s). The material in this document is subject to change in form and content after further study. The contributor(s) reserve(s) the right to add, amend or withdraw material contained herein. Release:The contributor acknowledges and accepts that this contribution becomes the property of IEEE and may be made publicly available by P

doc.: IEEE f Submission TG4f FM Deviation Tolerance March 2011 Paul Gorday, Sunrise Micro DevicesSlide 2

doc.: IEEE f Submission MSK Modulation 1 MSK is binary continuous-phase FSK with modulation index h=0.5 FM deviation = Δf = 0.25R b (R b = bit rate = 1/T b ) March 2011 Paul Gorday, Sunrise Micro DevicesSlide 3 Data Waveform Instantaneous Frequency 1 f c + Δf f c - Δf t t 2T b T b 3T b 4T b 5T b 7T b 6T b 8T b 2T b T b 3T b 4T b 5T b 7T b 6T b 8T b [1] John G. Proakis, Digital Communications, 3 rd Ed., McGraw-Hill, New York, 1995.

doc.: IEEE f Submission MSK Implementation Numerous implementation methods exist for FM Low-cost, low-power options are desired for f Examples include –Direct modulation of PLL reference oscillator –Frac-N synthesizer modulation March 2011 Paul Gorday, Sunrise Micro DevicesSlide 4 Frac-N Modulation Ref. Osc. Modulation FM Modulated Carrier Loop Filter Phase Det. OSCVCO Loop Divider

doc.: IEEE f Submission PLL Modulation Effects The PLL acts like a data filter (filtered MSK) → rounded bit edges, overshoot PLL response is constrained by other performance criteria (component size, phase noise, spurs, settling time). Practical PLL configuration results in 25-30% overshoot. March 2011 Paul Gorday, Sunrise Micro DevicesSlide 5 PLL settings: 400 kHz unity gain frequency, 7x ratio of loop filter pole/zero to unity gain frequency R b =31.25 kbpsR b =250 kbps

doc.: IEEE f Submission Packet Error Rate (PER) March 2011 Paul Gorday, Sunrise Micro DevicesSlide kbps: Negligible effect on PER 250 kbps: PER slightly improved due to deviation overshoot R b = 250 kbps

doc.: IEEE f Submission Spectrum March 2011 Paul Gorday, Sunrise Micro DevicesSlide kbps: Negligible effect on spectrum 250 kbps: Main lobe slightly wider, reduced side lobes (filtered MSK) R b =250 kbps

doc.: IEEE f Submission Recommendations Low cost and low power are main drivers for f To minimize cost and power, modulation specifications should be the least restrictive specifications that allow functional requirements of the standard to be met Transient deviation errors shown here don’t adversely affect performance Peak deviation tolerance spec of 30% allows low-cost, low- power implementation option Can also specify a tighter “steady state” deviation tolerance when data contains long pattern of “1’s” or “0’s”. March 2011 Paul Gorday, Sunrise Micro DevicesSlide 8