©2004 Brooks/Cole FIGURES FOR CHAPTER 10 INTRODUCTION TO VHDL Click the mouse to move to the next page. Use the ESC key to exit this chapter. This chapter.

Slides:

Advertisements

Similar presentations

UNIT 2: Data Flow description

Advertisements

HDL Programming Fundamentals

UNIT 8: Synthesis Basics

©2004 Brooks/Cole FIGURES FOR CHAPTER 16 SEQUENTIAL CIRCUIT DESIGN Click the mouse to move to the next page. Use the ESC key to exit this chapter. This.

©2004 Brooks/Cole FIGURES FOR CHAPTER 15 REDUCTION OF STATE TABLES STATE ASSIGNMENT Click the mouse to move to the next page. Use the ESC key to exit this.

©2004 Brooks/Cole FIGURES FOR CHAPTER 7 MULTI-LEVEL GATE CIRCUITS NAND AND NOR GATES Click the mouse to move to the next page. Use the ESC key to exit.

©2004 Brooks/Cole FIGURES FOR CHAPTER 12 REGISTERS AND COUNTERS Click the mouse to move to the next page. Use the ESC key to exit this chapter. This chapter.

©2004 Brooks/Cole FIGURES FOR CHAPTER 11 LATCHES AND FLIP-FLOPS Click the mouse to move to the next page. Use the ESC key to exit this chapter. This chapter.

©2004 Brooks/Cole FIGURES FOR CHAPTER 20 VHDL FOR DIGITAL SYSTEM DESIGN Click the mouse to move to the next page. Use the ESC key to exit this chapter.

©2004 Brooks/Cole FIGURES FOR CHAPTER 13 ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS Click the mouse to move to the next page. Use the ESC key to exit this.

©2004 Brooks/Cole FIGURES FOR CHAPTER 14 DERIVATION OF STATE GRAPHS AND TABLES Click the mouse to move to the next page. Use the ESC key to exit this chapter.

©2004 Brooks/Cole FIGURES FOR CHAPTER 17 VHDL FOR SEQUENTIAL LOGIC Click the mouse to move to the next page. Use the ESC key to exit this chapter. This.

1 Introduction to VHDL (Continued) EE19D. 2 Basic elements of a VHDL Model Package Declaration ENTITY (interface description) ARCHITECTURE (functionality)

EE 261 – Introduction to Logic Circuits

Introduction To VHDL for Combinational Logic

Supplement on Verilog adder examples

INTRO TO VHDL Appendix A: page page VHDL is an IEEE and ANSI standard. VHDL stands for Very High Speed IC hardware description language.

Combinational Logic with Verilog Materials taken from: Digital Design and Computer Architecture by David and Sarah Harris & The Essentials of Computer.

Multiplexers Section 3-7 Mano & Kime. Multiplexers & Demultiplexers Multiplexers (Selectors) Lab 1 – Behavioral VHDL -- Multiplexers MUX as a Universal.

©2005 Brooks/Cole - Thomson Learning FIGURES FOR CHAPTER 2 STATISTICAL INFERENCE Click the mouse or use the arrow keys to move to the next page. Use the.

FIGURES FOR CHAPTER 19 STATE MACHINE DESIGN WITH SM CHARTS

©2004 Brooks/Cole FIGURES FOR CHAPTER 9 MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES Click the mouse to move to the next page. Use the ESC key.

©2004 Brooks/Cole FIGURES FOR CHAPTER 1 INTRODUCTION Click the mouse to move to the next page. Use the ESC key to exit this chapter. This chapter in the.

1 VLSI DESIGN USING VHDL Part II A workshop by Dr. Junaid Ahmed Zubairi.

2-to-1 Multiplexer: if Statement Discussion D2.1 Example 4.

Introduction to VHDL VHDL Tutorial R. E. Haskell and D. M. Hanna T1: Combinational Logic Circuits.

Chapter 3 Continued Logic Gates Logic Chips Combinational Logic Timing Sequential Logic Flip Flops Registers Memory State Machines.

George Mason University ECE 448 – FPGA and ASIC Design with VHDL Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic ECE 448.

©2010 Cengage Learning Engineering. All Rights Reserved.10-0 Introduction to VHDL PowerPoint Presentation © Cengage Learning, Engineering. All Rights.

ECE 331 – Digital System Design Single-bit Adder Circuits and Adder Circuits in VHDL (Lecture #12) The slides included herein were taken from the materials.

Quad 2-to-1 Multiplexer Discussion D7.4 Example 7.

FIGURES FOR CHAPTER 1 INTRODUCTION NUMBER SYSTEMS AND CONVERSION

©2004 Brooks/Cole FIGURES FOR CHAPTER 18 CIRCUITS FOR ARITHMETIC OPERATIONS Click the mouse to move to the next page. Use the ESC key to exit this chapter.

Combinational Circuits Chapter 3 S. Dandamudi To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

©2004 Brooks/Cole FIGURES FOR CHAPTER 4 APPLICATIONS OF BOOLEAN ALGEBRA MINTERM AND MAXTERM EXPANSIONS Click the mouse to move to the next page. Use the.

VHDL TUTORIAL Preetha Thulasiraman ECE 223 Winter 2007.

Digital Logic Structures: Chapter 3 COMP 2610 Dr. James Money COMP

Basic Overview of VHDL Matthew Murach Slides Available at:

Introducing the Nexys 2 Board CS 332 – Operating Systems 12/04/2011 by Otto Castell-R.

ECE 331 – Digital System Design Single-bit Adder Circuits and Adder Circuits in VHDL (Lecture #11) The slides included herein were taken from the materials.

M. Balakrishnan Dept of Computer Science & Engg. I.I.T. Delhi

Hardware languages "Programming"-language for modelling of (digital) hardware 1 Two main languages: VHDL (Very High Speed Integrated Circuit Hardware Description.

CEC 220 Digital Circuit Design Introduction to VHDL Wed, February 25 CEC 220 Digital Circuit Design Slide 1 of 19.

Digital System Projects

Logic Gates M. AL-Towaileb1. Introduction Boolean algebra is used to model the circuitry of electronic devices. Each input and each output of such a device.

04/26/20031 ECE 551: Digital System Design & Synthesis Lecture Set : Introduction to VHDL 12.2: VHDL versus Verilog (Separate File)

Apr. 3, 2000Systems Architecture I1 Introduction to VHDL (CS 570) Jeremy R. Johnson Wed. Nov. 8, 2000.

VHDL ELEC 311 Digital Logic and Circuits Dr. Ron Hayne Images Courtesy of Cengage Learning.

CEC 220 Digital Circuit Design Introduction to VHDL Friday, February 21 CEC 220 Digital Circuit Design Slide 1 of 10.

May 9, 2001Systems Architecture I1 Systems Architecture I (CS ) Lab 5: Introduction to VHDL Jeremy R. Johnson May 9, 2001.

Lecture #10 Page 1 Lecture #10 Agenda 1.VHDL : Concurrent Signal Assignments 2.Decoders using Structural VHDL Announcements 1.HW #4 due 2.HW #5 assigned.

CEC 220 Digital Circuit Design Introduction to VHDL Wed, Oct 14 CEC 220 Digital Circuit Design Slide 1 of 19.

Instructor: Oluwayomi Adamo Digital Systems Design.

IAY 0600 Digital Systems Design VHDL discussion Structural style Modular design and hierarchy Part 1 Alexander Sudnitson Tallinn University of Technology.

Combinational logic circuit

Structural style Modular design and hierarchy Part 1

FIGURES FOR CHAPTER 1 GETTING STARTED

This chapter in the book includes: Objectives Study Guide

CHAPTER 17 VHDL FOR SEQUENTIAL LOGIC

SLIDES FOR CHAPTER 12 REGISTERS AND COUNTERS

Combinatorial Logic Design Practices

CHAPTER 10 Introduction to VHDL

Logic Gates L Al-zaid Math110.

ECE 448 Lecture 3 Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic ECE 448 – FPGA and ASIC Design with VHDL.

Hardware Descriptive Languages these notes are taken from Mano’s book

Data Flow Description of Combinational-Circuit Building Blocks

Logic Gates Dr.Halimah Alshehri.

This chapter in the book includes: Objectives Study Guide

Chapter 10 Introduction to VHDL

Presentation transcript:

©2004 Brooks/Cole FIGURES FOR CHAPTER 10 INTRODUCTION TO VHDL Click the mouse to move to the next page. Use the ESC key to exit this chapter. This chapter in the book includes: Objectives Study Guide 10.1VHDL Description of Combinational Circuits 10.2VHDL Models for Multiplexers 10.3VHDL Modules 10.4Signals and Constants 10.5Arrays 10.6VHDL Operators 10.7Packages and Libraries 10.8IEEE Standard Logic 10.9Compilation and Simulation of VHDL Code Problems

©2004 Brooks/Cole Figure 10-1: Gate Circuit

©2004 Brooks/Cole Figure 10-2: Inverter with Feedback

©2004 Brooks/Cole Figure 10-3: Three Gates with a Common Input and Different Delays

©2004 Brooks/Cole Figure 10-4: Array of AND Gates

©2004 Brooks/Cole Figure 10-5: 2-to-1 Multiplexer

©2004 Brooks/Cole Figure 10-6: Cascaded 2-to-1 MUXes

©2004 Brooks/Cole Figure 10-7: 4-to-1 Multiplexer

©2004 Brooks/Cole Figure 10-8: VHDL Module with Two Gates

©2004 Brooks/Cole Figure 10-9: VHDL Program Structure

©2004 Brooks/Cole Figure 10-10: Full Adder Module architecture Equations of FullAdder is begin-- concurrent assignment statements Sum <= X xor Y xor Cin after 10 ns; Cout <= (X and Y) or (X and Cin) or (Y and Cin) after 10 ns; end Equations ; entity FullAdder is port (X,Y,Cin: in bit; --Inputs Cout, Sum: out bit);--Outputs end FullAdder;

©2004 Brooks/Cole Figure 10-11: 4-Bit Binary Adder

©2004 Brooks/Cole Figure 10-12: Structural Description of a 4-Bit Adder

©2004 Brooks/Cole Section 10.3, p. 271

©2004 Brooks/Cole Figure 10-13: VHDL Description of a ROM 1entity ROM9_17 is 2port (A, B, C: in bit; F: out bit_vector(0 to 3)); 3end entity; 4architecture ROM of ROM9_17 is 5type ROM8X4 is array (0 to 7) of bit_vector(0 to 3); 6constant ROM1: ROM8X4 := ("1010", "1010", "0111","0101", "1100", "0001", "1111", "0101"); 7signal index: Integer range 0 to 7; 8begin 9Index <= vec2int(A&B&C); -- A&B&C Is a 3-bit vector 10-- vec2int is a function that converts this vector to an integer 11F <= ROM1 (index); 12-- this statement reads the output from the ROM 13end ROM;

©2004 Brooks/Cole Figure 10-14: Comparator for Integers

©2004 Brooks/Cole Figure 10-15: NOR-NOR Circuit and Structural VHDL Code Using Library Components

©2004 Brooks/Cole Figure 10-16: Tri-State Buffer

©2004 Brooks/Cole Figure 10-17: Tri-State Buffers Driving a Bus

©2004 Brooks/Cole Figure 10-18: Resolution Function for Two Signals

©2004 Brooks/Cole Figure 10-19: VHDL Code for Binary Adder

©2004 Brooks/Cole Figure 10-20: VHDL Code for Bi-Directional I/O Pin entity IC_pin is port(IO_pin: inout std_logic); end entity; architecture bi_dir of IC_pin is component IC port(input: in std_logic; output: out std_logic); end component; signal input, output, en: std_logic; begin -- connections to bi-directional I/O pin IO_pin <= output when en = '1' else 'Z'; input <= IO_pin; IC1: IC port map (input, output); end bi_dir;

©2004 Brooks/Cole Figure 10-21: Compilation, Simulation, and Synthesis of VHDL Code

©2004 Brooks/Cole Figure 10-22: Simulation of VHDL Code