MICROWAVE FET Microwave FET : operates in the microwave frequencies unipolar transistors current flow is carried out by majority carriers alone It’s a voltage controlled device voltage at the gate terminal controls the current flow.

Advantages of FET’s compared to BJT It has voltage gain in addition to current gain Efficiency is higher Noise figure is low Input resistance is very high, upto megaohms. Operating frequency is upto X band/

Physical Structure

N-channel JFET: N-type material is sandwiched between 2 highly doped of p-type material (p+ regions) If the middle part is a p-type semiconductor, then its p-channel JFET. 2 p-type regions in the n channel JFET – Gates Each end on n-channel is joined by a metallic contact. Source : Contact which supplies source of the flowing electrons Drain :Contact which drains electrons out of the material Id : flows from drain to the device For p-channel JFET, polarities of Vg & Vd are interchanged. Electrons have higher mobility n-channel JFET provides higher conductivity. Higher speed

Operation Under normal conditions, Vg = zero, Id = zero. Channel between gate junctions is entirely open. When Vd is applied n-type semiconductor bar acts as resistor current Id increases linearly with Vg For p-channel JFET, polarities of Vg & Vd are interchanged. As Vd is further increased majority of free electrons get depleted from the channel. Space chare extends into the channel. space charge regions expand & join together. All the free electrons are completely depleted in the joined region -> PINCH OFF If Vg is applied : pinch off voltage reduces

I-V CHARACTERISTICS

Pinch off Voltage It is the gate reverse voltage that removes all the free charges from the channel. Poisson’s equation for the voltage in n-channel

Integrating the above equation and applying boundary condition ie Integrating the above equation and applying boundary condition ie. E=0 at y=a yield Integrating once again and applying boundary condition V=0 at y=0 yield

(a : the height of the channel in metres) Pinch off voltage under saturation condition is

The N-channel resistance

Substitution and rearrangement gives

BREAKDOWN REGION As Vd increases for a constant Vg, the bias voltage causes avalanche breakdown across the junction. Drain current Id increases sharply. The breakdown voltage is

MOSFETs- Metal Oxide Semiconductor Field Effect Transistors 4 terminal – Source, Gate, Drain and Substrate Simple structure and economic Types NMOS PMOS CMOS Current is controlled by electric field : Junction Field Effect Transistors

PHYSICAL STRUCTURES

N-CHANNEL MOSFET P-type substrate 2 highly doped n regions diffused – source & drain separated by 0.5um Thin layer of silicon dioxide grown over the surface. Metal contact on the insulator – acts as gate.

Electronic Mechanism No gate voltage applied connection b/w source & drain : 2 back to back pn junctions Reverse leakage current b/w Drain and Source Gate voltage is +ve w.r.t. Source. Positive charge deposition on the gate metal Negative charges are induced in the p-substrate at the semiconductor-insulator interface Formation of channel  conduction of Id Threshold Voltage : Minimum gate voltage for channel formation

Modes of Operation Enhancement Mode Normally off mode Gate voltage = 0 V Very low Channel conductance Considered as the OFF state Positive gate voltage to turn on the device Channel length is “Enhanced” Application : As Linear Power Amplifiers

Depletion Mode Normally ON mode A channel is present even at zero bias To turn off the device  Negative gate voltage “Depletion” of charge carriers by the application of negative gate voltage

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