1 Noordwijk April 23-/24 2012 April 2012 Summary for Plenary Abraham Arceo (Sematech) Arnaud Favre (adixen) Herve Fontaine (CEA Leti) Guillaume Gallet.

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Presentation transcript:

1 Noordwijk April 23-/ April 2012 Summary for Plenary Abraham Arceo (Sematech) Arnaud Favre (adixen) Herve Fontaine (CEA Leti) Guillaume Gallet (Camfil Farr) Astrid Gettel (GlobalFoundries) Jost Kames (artemis control) Slava Libman (Balazs NanoAnalysis, Air Liquide) Andreas Neuber (AMAT) Lothar Pfitzner (Fraunhofer IISB) Koichiro Saga (Sony Corporation)

2 Noordwijk April 23-/ APRIL 2012 Summary for Plenary Discussion of the agenda and of the structure of YE/CIA (characterization, inspection, analysis) Presentation of “Predictive Sampling” YE Roadmap for More-than-Moore Discussion of need of YL for 450mm Telecon with Japanese YE: Discussion of the scope of the chapter on CIA -Potential new tables and key challenges -It is obvious that contributors with product engineering related expertise are the key to design the new meaningful tables / requirements. JEITA will start the activity with contributors from the other areas. Process, Device, Chip, System Level -Confirmation of collaboration on the new structure -Assignment of YE subchapter: scope of work is defined as follows: -WECCaround wafer /above wafer issues -CIAtool specification on the wafer /in the wafer issues Based on this, CIA may include the device/chip/system level issue Requirements of PFA (Physical Failure Analysis) will be discussed later Alignment of WECC approach Cross-TWG Meetings:, Litho, Metrology, FEP, A&P, Factory, Interconnect

3 Noordwijk April 23-/ Discussion of the near term challenges and their importance: –Detection of organic contamination on surfaces – The detection and speciation of nonvolatile organics on surfaces is currently not possible in the fab. There is no laboratory scale instrumentation available. –Non-Visual Defects and Process Variations – Increasing yield loss due to non-visual defects and process variations requires new approaches in methodologies, diagnostics and control. This includes the correlation of systematic yield loss and layout attributes. The irregularity of features in logic areas and pattern density difference in memory cell array makes them very sensitive to systematic yield loss mechanisms such as patterning