T.J. Kazmierski Circuit-level modelling of carbon nanotube field-effect transistors 1 MOS-AKMunich 14 September 2007 School of Electronics and Computer.

Slides:



Advertisements
Similar presentations
ECSE-6230 Semiconductor Devices and Models I Lecture 4
Advertisements

Chapter 0 Review of Algebra.
Chapter 6 Matrix Algebra.
Lecture 2 Operational Amplifiers
Chapter 2-4. Equilibrium carrier concentrations
Agenda Semiconductor materials and their properties PN-junction diodes
Chapter 2-3. States and carrier distributions
Lecture 6 Solid-State Diodes and Diode Circuits
0 - 0.
Addition Facts
Experimental Particle Physics PHYS6011 Joel Goldstein, RAL 1.Introduction & Accelerators 2.Particle Interactions and Detectors (2) 3.Collider Experiments.
Chapter 7 Sampling and Sampling Distributions
DEPARTMENT OF CIVIL ENGINEERING THE NATIONAL UNIVERSITY OF SINGAPORE Euro-SiBRAM2002 International Colloquium Prague - Czech Republic June 24 to 26, 2002.
Announcements Homework 6 is due on Thursday (Oct 18)
Spoofing State Estimation
A Stabilization Technique for Phase-Locked Frequency Synthesizers Tai-Cheng Lee and Behzad Razavi IEEE Journal of Solid-State Circuits, Vol. 38, June 2003.
Notes 15 ECE Microwave Engineering
P. Venkataraman Mechanical Engineering P. Venkataraman Rochester Institute of Technology DETC2012 – 70343: A Robust Technique for Lumped Parameter Inverse.
An Advanced Shell Theory Based Tire Model by D. Bozdog, W. W. Olson Department of Mechanical, Industrial and Manufacturing Engineering The 23 rd Annual.
Author: Chengchen, Bin Liu Publisher: International Conference on Computational Science and Engineering Presenter: Yun-Yan Chang Date: 2012/04/18 1.
Discrete Controller Design
An Introduction to Matching and Layout Alan Hastings Texas Instruments
Compact IGBT Modelling for System Simulation Philip Mawby Angus Bryant.
Embedded Systems Design: A Unified Hardware/Software Introduction 1 Chapter 10: IC Technology.
Imperial College London 1 3. Beam extraction 3. Extraction of particle beams 3.1 The space charge limit and Child-Langmuirs law 3.2 External and internal.
Variation Aware Gate Delay Models Dinesh Ganesan.
ECA1212 Introduction to Electrical & Electronics Engineering Chapter 6: Field Effect Transistor by Muhazam Mustapha, October 2011.
Transistors: Building blocks of electronic computing Lin Zhong ELEC101, Spring 2011.
1 Computer Programming Boolean Logic Copyright © Texas Education Agency, 2013.
Introduction to MOSFETs
R. van Langevelde, A.J. Scholten Philips Research, The Netherlands
1 Analysis of Random Mobility Models with PDE's Michele Garetto Emilio Leonardi Politecnico di Torino Italy MobiHoc Firenze.
Solving Equations How to Solve Them
1 Directed Depth First Search Adjacency Lists A: F G B: A H C: A D D: C F E: C D G F: E: G: : H: B: I: H: F A B C G D E H I.
Arc-length computation and arc-length parameterization
1 Chapter 5-1. PN-junction electrostatics You will also learn about: Poisson’s Equation Built-In Potential Depletion Approximation Step-Junction Solution.
T H E U N I V E R S I T Y O F B R I T I S H C O L U M B I A 1 September 2005MC-SSL Simulation 1 Analysis of Scalable Security – MC-SSL Simulation Reducing.
Past Tense Probe. Past Tense Probe Past Tense Probe – Practice 1.
Atomistic Simulation of Carbon Nanotube FETs Using Non-Equilibrium Green’s Function Formalism Jing Guo 1, Supriyo Datta 2, M P Anantram 3, and Mark Lundstrom.
1 General Iteration Algorithms by Luyang Fu, Ph. D., State Auto Insurance Company Cheng-sheng Peter Wu, FCAS, ASA, MAAA, Deloitte Consulting LLP 2007 CAS.
Addition 1’s to 20.
Running a model's adjoint to obtain derivatives, while more efficient and accurate than other methods, such as the finite difference method, is a computationally.
Test B, 100 Subtraction Facts
An Adaptive System for User Information needs based on the observed meta- Knowledge AKERELE Olubunmi Doctorate student, University of Ibadan, Ibadan, Nigeria;
Week 1.
Dantzig-Wolfe Decomposition
Using Cramer-Rao-Lower-Bound to Reduce Complexity of Localization in Wireless Sensor Networks Dominik Lieckfeldt, Dirk Timmermann Department of Computer.
© Electronics ECE 1231 Recall-Lecture 3 Current generated due to two main factors Drift – movement of carriers due to the existence of electric field Diffusion.
Nonlinear Compact Thermal Model of SiC Power Semiconductor Devices Krzysztof Górecki, Janusz Zarębski, Damian Bisewski and Jacek Dąbrowski Department of.
The nonlinear compact thermal model of power MOS transistors
Physical structure of a n-channel device:
COMPACT MODEL FOR LONG-CHANNEL SYMMETRIC DOPED DG COMPACT MODEL FOR LONG-CHANNEL SYMMETRIC DOPED DG Antonio Cerdeira 1, Oana Moldovan 2, Benjamín Iñiguez.
EE466: VLSI Design Lecture 02 Non Ideal Effects in MOSFETs.
MCE 561 Computational Methods in Solid Mechanics
EE415 VLSI Design The Devices: Diode [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]
Semiconductor Devices III Physics 355. Transistors in CPUs Moore’s Law (1965): the number of components in an integrated circuit will double every year;
Extension for High-Voltage Lateral DMOS Transistors
ECE 342 Electronic Circuits 2. MOS Transistors
EXAMPLE 6.1 OBJECTIVE Fp = 0.288 V
Simulation of transport in silicon devices at atomistic level Introduction Properties of homogeneous silicon Properties of pn junction Properties of MOSFET.
Junction Capacitances The n + regions forms a number of planar pn-junctions with the surrounding p-type substrate numbered 1-5 on the diagram. Planar junctions.
Digital Integrated Circuits© Prentice Hall 1995 Devices Jan M. Rabaey The Devices.
Introduction to semiconductor technology. Outline –7 Field effect transistors MOS transistor ”current equation" MOS transistor channel mobility Substrate.
BASIC SEMICONDUCTOR ELECTRONIC CIRCUITS Introduction of two basic electronic elements: diode and transistor LEARNING GOALS Diodes structure and four modeling.
Norhayati Soin 06 KEEE 4426 WEEK 3/2 20/01/2006 KEEE 4426 VLSI WEEK 4 CHAPTER 1 MOS Capacitors (PART 3) CHAPTER MOS Capacitance.
Nano and Giga Challenges in Microelectronics Symposium and Summer School Research and Development Opportunities Cracow Sep , 2004 Afternoon 4: Carbonanotubes.
Review for Final Exam MOSFET and BJT Basis of amplifiers
Lecture 7 DFT Applications
Numerical Analysis Lecture 7.
Channel Length Modulation
Presentation transcript:

T.J. Kazmierski Circuit-level modelling of carbon nanotube field-effect transistors 1 MOS-AKMunich 14 September 2007 School of Electronics and Computer Science Southampton University Circuit-level modelling of carbon nanotube field-effect transistors Tom J Kazmierski School of Electronic and Computer Science University of Southampton, United Kingdom

T.J. Kazmierski Circuit-level modelling of carbon nanotube field-effect transistors 2 MOS-AKMunich 14 September 2007 School of Electronics and Computer Science Southampton University Outline oIntroduction  New efficient methodology for numerical CNT FET modelling based on piece-wise non-linear approximation oPNL modelling of non-equilibrium mobile charge density  Two PNL approximations leading to closed-form solution of self- consistent voltage equation oDrain current calculation oEquivalent circuit oSimulation experiments demonstrating speed up and modelling accuracy oConclusion: what next?

T.J. Kazmierski Circuit-level modelling of carbon nanotube field-effect transistors 3 MOS-AKMunich 14 September 2007 School of Electronics and Computer Science Southampton University Introduction oCNT FET theory and operation are gradually better understood. oEarly CNT FET models simply used MOS equations – no good. oNow a physical theory of ballistic CNT transport exists. oCircuit-level models have been developed based on theory but they are very complex in terms of computational intensity. oRecently fast models appeared, based on numerical approximation. oFocus of this talk: new, efficient piecewise non-linear approximation of mobile charge  three orders of magnitude faster than evaluation of physical equations, but still maintaining high accuracy. oImportant for circuit design where very large numbers of CNT devices will need to be simulated.

T.J. Kazmierski Circuit-level modelling of carbon nanotube field-effect transistors 4 MOS-AKMunich 14 September 2007 School of Electronics and Computer Science Southampton University Non-equilibrium mobile charge oNon-equilibrium mobile charge is injected into CNT when drain-source voltage is applied: oState densities are determined by Fermi-Dirac probability distribution: V SC – self-consistent voltage

T.J. Kazmierski Circuit-level modelling of carbon nanotube field-effect transistors 5 MOS-AKMunich 14 September 2007 School of Electronics and Computer Science Southampton University Self-consistent voltage equation V SC - recently introduced concept Strongly non-linear, requires Newton-Raphson iterations and calculation of integrals – standard approach to CNT FET modelling Total charge at terminal capacitances Total terminal capacitance

T.J. Kazmierski Circuit-level modelling of carbon nanotube field-effect transistors 6 MOS-AKMunich 14 September 2007 School of Electronics and Computer Science Southampton University Standard approaches to evaluate charge density oNewton-Raphson technique and finite integration oNon-equilibrium Green’s function (NEGF) oRecently piece-wise linear and piece-wise non-linear approximations have been proposed to obtain closed- form symbolic solutions  The aim is to eliminate the need for computationally intensive iterative calculations in development of models for circuit simulators

T.J. Kazmierski Circuit-level modelling of carbon nanotube field-effect transistors 7 MOS-AKMunich 14 September 2007 School of Electronics and Computer Science Southampton University Total drain current If V SC is known, total drain current can be obtained form Fermi-Dirac statistics directly: Closed-form solution for Fermi-Dirac integral of order 0 exists: hence:

T.J. Kazmierski Circuit-level modelling of carbon nanotube field-effect transistors 8 MOS-AKMunich 14 September 2007 School of Electronics and Computer Science Southampton University Circuit model of a top-gate CNT FET If equal portions of the equilibrium charge qN 0 are allocated to drain and source, non-equilibrium charges at drain and source can be modelled as non-linear capacitances. A hypothetical inner node can be created to represent the self-consistent potential

T.J. Kazmierski Circuit-level modelling of carbon nanotube field-effect transistors 9 MOS-AKMunich 14 September 2007 School of Electronics and Computer Science Southampton University New technique to accelerate VSC calculation Model 1: 3-piece non-linear approximation of charge density: solid line: theory dashed-line: approximation Linear and quadratic pieces

T.J. Kazmierski Circuit-level modelling of carbon nanotube field-effect transistors 10 MOS-AKMunich 14 September 2007 School of Electronics and Computer Science Southampton University New technique to accelerate VSC calculation Model 2: 4-piece non-linear approximation: solid line: theory dashed-line: approximation Region boundaries are optimised for best fit Linear, quadratic and 3 rd order pieces

T.J. Kazmierski Circuit-level modelling of carbon nanotube field-effect transistors 11 MOS-AKMunich 14 September 2007 School of Electronics and Computer Science Southampton University Speed-up due to PNL approximation FETToy – reference theoretical model implemented in MATLAB CPU times for PNL Model 1 and Model 2 obtained also from a MATLAB script Model 1 runs 3500 faster and Model 2 – 1100 times

T.J. Kazmierski Circuit-level modelling of carbon nanotube field-effect transistors 12 MOS-AKMunich 14 September 2007 School of Electronics and Computer Science Southampton University Loss of accuracy due to PNL approximation Model 1 – dashed, FETToy - solid Typical parameters: T=300K, Ef = -0.32eV Model 2 – dashed, FETToy - solid

T.J. Kazmierski Circuit-level modelling of carbon nanotube field-effect transistors 13 MOS-AKMunich 14 September 2007 School of Electronics and Computer Science Southampton University RMS errors for Ef=-0.32eV Model 2 accurate within 2%, Model 1 – 4.6%, at T=300K

T.J. Kazmierski Circuit-level modelling of carbon nanotube field-effect transistors 14 MOS-AKMunich 14 September 2007 School of Electronics and Computer Science Southampton University Accuracy at extreme temperatures and Fermi levels Model 1 – dashed, FETToy - solid Extreme parameters: T=150K, Ef = 0eV Model 2 – dashed, FETToy - solid

T.J. Kazmierski Circuit-level modelling of carbon nanotube field-effect transistors 15 MOS-AKMunich 14 September 2007 School of Electronics and Computer Science Southampton University Accuracy at extreme temperatures and Fermi levels (2) Model 1 – dashed, FETToy - solid Extreme parameters: T=450K, Ef = -0.5eV Model 2 – dashed, FETToy - solid

T.J. Kazmierski Circuit-level modelling of carbon nanotube field-effect transistors 16 MOS-AKMunich 14 September 2007 School of Electronics and Computer Science Southampton University RMS errors for Ef=-0.5eV Across T and E F ranges - Model 2 is accurate within 2.8%, Model 1 – 4.8%

T.J. Kazmierski Circuit-level modelling of carbon nanotube field-effect transistors 17 MOS-AKMunich 14 September 2007 School of Electronics and Computer Science Southampton University RMS errors for Ef=0eV

T.J. Kazmierski Circuit-level modelling of carbon nanotube field-effect transistors 18 MOS-AKMunich 14 September 2007 School of Electronics and Computer Science Southampton University Conclusion oNew, fast, numerical CN FET model has been proposeds oSuitable for a direct implementation in SPICE-like circuit-level simulators oFurther evidence to support suggestions that costly Newton- Raphson iterations and Fermi-Dirac integral calculations can be avoided leading to a substantial speed-up. oTwo models proposed and tested in simulationss oFuture work will involve CN FET analysis of speed and modelling accuracy of circuit structures built of CN FETs.