Baloch 1MAPLD 2005/1024-L Design of a ‘Single Event Effect’ Mitigation Technique for Reconfigurable Architectures SAJID BALOCH Prof. Dr. T. Arslan 1,2 Dr.Adrian Stoica 3 Supervisory Team

Baloch 2MAPLD 2005/1024-L ACRONYMES –SEU (Single Event Effect) –SET (Single Event Transient) –SEB (Single Event Burnout) –SEL (Single Event Latch-up) –Cfg (Configuration) –EDAC (Error Detection and Correction) –SoC (System on Chip) –FPGA (Field Programmable Gate Array) –DEU (Double Event Upset) –TEU (Triple Event Upset ) –MEU (Multiple Event Upsets)

Baloch 3MAPLD 2005/1024-L RECONFIGURABLE ARCHITECTURES Re-Configurable SoC Architecture a)FPGAs - SRAM - Anti Fuse - EPROM b) Reconfigurable SoC - General purpose - Domain Specific

Baloch 4MAPLD 2005/1024-L RADIATION EFFECTS RE-CONFIGURABLE ARCHITECTURES –PERMANANT FAULTS (due to SEL, SEB etc) –TEMPORARY FAULTS (due to SEU etc)

Baloch 5MAPLD 2005/1024-L SEU MITIGATION TECHNIQUES a)HARDWARE REDUNDANCY - Dual Modular Redundancy (DMR) - Triple Modular Redundancy (TMR) - EDAC Codes - Process Technology b) TIME REDUNDANCY c) COMBINATION (Hardware & Time)

Baloch 6MAPLD 2005/1024-L TRANSIENT FAULTS (Data Memory etc) PERMANANT FAULTS (Cfg. Memory ) Radiation Hardening SEU EFFECTS

Baloch 7MAPLD 2005/1024-L SEU EFECTS Synchronous Circuits

Baloch 8MAPLD 2005/1024-L SEU EFECTS Configuration Memory

Baloch 9MAPLD 2005/1024-L SEU EFECTS ROUTING OF A SIGNAL

Baloch 10MAPLD 2005/1024-L Proposed SEU/SET Mitigation Technique based on: Temporal Data Sampling Weighted Voting Salient Features of The Proposed Technique: Auto Correction Mechanism for 100% SEU Recovery 100% Double Fault Recovery Voter Faults Recovery

Baloch 11MAPLD 2005/1024-L Temporal Sampling Primary Section Secondary Section

Baloch 12MAPLD 2005/1024-L TEMPORAL SAMPLING Clock Scheme 3 derivates of Main Clock Each Clock is Phase shifted 25% duty Cycle

Baloch 13MAPLD 2005/1024-L Minimized Term X4.X3.X0 + X5.X3.X0 + X5.X4.X0 + X4.X3.X1 + X5.X3.X1 + X5.X4.X1 + X4.X3.X2 + X5.X3.X2 + X5.X4.X2 + X5.X4.X3 + X3.X2.X1.X0 + X4.X2.X1.X0 + X5.X2.X1.X0 Weighted Voter Circuit

Baloch 14MAPLD 2005/1024-L SEU in Secondary Section NodeBefore SEU After SEU Voting Weights ‘1’ ‘0’ Total Votes ‘1’ ‘0’ Case Example

Baloch 15MAPLD 2005/1024-L Multiple Bit Upset NodeBefore SEU After SEU Voting Weights ‘1’ ‘0’ Total Votes ‘1’ ‘0’ Case Example

Baloch 16MAPLD 2005/1024-L Hardware Implementation of Proposed Scheme with Auto-Correction Mechanism

Baloch 17MAPLD 2005/1024-L Single Event Transition Fault Data / Clock

Baloch 18MAPLD 2005/1024-L SEU/SET Simulator SEU’s can be injected at instance SEU of any duration can be injected Multiple upsets can be injected

Baloch 19MAPLD 2005/1024-L Performance Analysis Fault Coverage Mitigation Scheme %age Fault Tolerance SETSEUDEUTEU Proposed Scheme100% 50% F. Lima etal Scheme63%100%-- D. Mavis etal Scheme100% 32%18%

Baloch 20MAPLD 2005/1024-L Performance Analysis Area Overhead Results are based on: 0.13µm CMOS technology