IC TESTING.

Slides:

Advertisements

Similar presentations

Digital Integrated Circuits© Prentice Hall 1995 Design Methodologies Design for Test.

Advertisements

The scale of IC design Small-scale integrated, SSI: gate number usually less than 10 in a IC. Medium-scale integrated, MSI: gate number ~10-100, can operate.

Chapter 3 Fault Modeling

DESIGN FOR TESTABILITY FAULT DETECTION TECHNIQUES

1 Dictionary-Less Defect Diagnosis as Surrogate Single Stuck-At Faults Chidambaram Alagappan Vishwani D. Agrawal Department of Electrical and Computer.

CMP238: Projeto e Teste de Sistemas VLSI Marcelo Lubaszewski Aula 2 - Teste PPGC - UFRGS 2005/I.

Slides based on Kewal Saluja

March 23, 2001VLSI Test: Bushnell-Agrawal/Lecture 211 Lecture 21 I DDQ Current Testing n Definition n Faults detected by I DDQ tests n Vector generation.

Lecture 11: Sequential Circuit Design. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 11: Sequential Circuits2 Outline  Sequencing  Sequencing Element Design.

LEONARDO INSIGHT II / TAP-MM ASTEP - Basic Test Concepts © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)1 Basic test concepts J. M. Martins.

9. Fault Modeling Reliable System Design 2011 by: Amir M. Rahmani.

Copyright 2001, Agrawal & BushnellDay-1 AM-3 Lecture 31 Testing Analog & Digital Products Lecture 3: Fault Modeling n Why model faults? n Some real defects.

Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 19alt1 Lecture 19alt I DDQ Testing (Alternative for Lectures 21 and 22) n Definition n Faults detected.

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 211 Lecture 21 I DDQ Current Testing n Definition n Faults detected by I DDQ tests n Vector generation.

EE466: VLSI Design Lecture 17: Design for Testability

Logic Simulation 4 Outline –Fault Simulation –Fault Models –Parallel Fault Simulation –Concurrent Fault Simulation Goal –Understand fault simulation problem.

Design for Testability

Output Hazard-Free Transition Tests for Silicon Calibrated Scan Based Delay Testing Adit D. Singh Gefu Xu Auburn University.

Lecture 5 Fault Modeling

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 51 Lecture 5 Fault Modeling n Why model faults? n Some real defects in VLSI and PCB n Common fault.

1 Introduction VLSI Testing. 2 Overview First digital products (mid 1940's) Complexity:low MTTF:hours Cost:high Present day products (mid 1980's) Complexity:high.

Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)1 Basic test concepts J. M. Martins Ferreira FEUP / DEEC - Rua Dr.

Testing of Logic Circuits. 2 Outline  Testing –Logic Verification –Silicon Debug –Manufacturing Test  Fault Models  Observability and Controllability.

Laboratory of Reliable Computing Department of Electrical Engineering National Tsing Hua University Hsinchu, Taiwan Delay Defect Characteristics and Testing.

Fundamentals of Electrical Testing

4/26/05Cheng: ELEC72501 A New Method for Diagnosing Multiple Stuck- at-Faults using Multiple and Single Fault Simulations An-jen Cheng ECE Dept. Auburn.

Digital Systems: Combinational Logic Circuits Digital IC Characteristics Wen-Hung Liao, Ph.D.

Digital Integrated Circuits© Prentice Hall 1995 Inverter THE INVERTERS.

Digital Systems: Digital IC Characteristics

ECE 553: TESTING AND TESTABLE DESIGN OF DIGITAL SYSTES Fault Modeling.

EE 447/EE547 1 VLSI DESIGN Lecture 10 Design for Testability.

Technical University Tallinn, ESTONIA 1 Boolean derivatives Calculation of the Boolean derivative: Given:

MOS Transistors The gate material of Metal Oxide Semiconductor Field Effect Transistors was original made of metal hence the name. Present day devices’

Introduction to CMOS VLSI Design Test. CMOS VLSI DesignTestSlide 2 Outline  Testing –Logic Verification –Silicon Debug –Manufacturing Test  Fault Models.

CSE477 L28 DFT.1Irwin&Vijay, PSU, 2003 CSE477 VLSI Digital Circuits Fall 2003 Lecture 28: Design for Test Mary Jane Irwin ( )

Unit I Testing and Fault Modelling

ECE 7502 Project Final Presentation

LOGIC GATES. Electronic digital circuits are also called logic circuits because with the proper input, they establish logical manipulation paths. Each.

Page 1EL/CCUT T.-C. Huang Mar TCH CCUT Introduction to IC Test Tsung-Chu Huang ( 黃宗柱 ) Department of Electronic Eng. Chong Chou Institute of Tech.

ECE 260B – CSE 241A Testing 1http://vlsicad.ucsd.edu ECE260B – CSE241A Winter 2005 Testing Website:

1 Note on Testing for Hardware Components. 2 Steps in successful hardware design (basic “process”): 1.Understand the requirements (“product’) 2.Write.

Fault Models, Fault Simulation and Test Generation Vishwani D. Agrawal Department of ECE, Auburn University Auburn, AL 36849, USA

TOPIC : Different levels of Fault model UNIT 2 : Fault Modeling Module 2.1 Modeling Physical fault to logical fault.

EE434 ASIC & Digital Systems Partha Pande School of EECS Washington State University

Terminal Impedances Eq Eq Eq

An introduction to Fault Detection in Logic Circuits By Dr. Amin Danial Asham.

CS/EE 3700 : Fundamentals of Digital System Design

Abdul-Rahman Elshafei – ID  Introduction  SLAT & iSTAT  Multiplet Scoring  Matching Passing Tests  Matching Complex Failures  Multiplet.

Manufacture Testing of Digital Circuits

Jan. 26, 2001VLSI Test: Bushnell-Agrawal/Lecture 51 Lecture 5 Fault Modeling n Why model faults? n Some real defects in VLSI and PCB n Common fault models.

TOPIC : Introduction to Faults UNIT 2: Modeling and Simulation Module 1 : Logical faults due to physical faults.

TOPIC : Fault detection and fault redundancy UNIT 2 : Fault modeling Module 2.3 Fault redundancy and Fault collapsing.

TOPIC : Introduction to Faults UNIT 2: Modeling and Simulation Module 1 : Logical faults due to physical faults.

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 51 Lecture 5 Fault Modeling n Why model faults? n Some real defects in VLSI and PCB n Common fault.

Formal Verification of Clock Domain Crossing Using Gate-level Models of Metastable Flip-Flops Ghaith Tarawneh, Andrey Mokhov and Alex Yakovlev Newcastle.

CUHK Test and Fault-Tolerance for Timing Error Presenter: Feng Yuan.

Lecture 5: Design for Testability. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 12: Design for Testability2 Outline  Testing –Logic Verification –Silicon.

Ch.4 Combinational Logic Circuits

Integrated Circuits.

COUPING WITH THE INTERCONNECT

Lecture 12: Design for Testability

ELEC Digital Logic Circuits Fall 2014 Logic Testing (Chapter 12)

Electrical Rules Check

Lecture 12: Design for Testability

Design for Testability

Lecture 5 Fault Modeling

Lecture 12: Design for Testability

Topics Switch networks. Combinational testing..

VLSI Testing Lecture 3: Fault Modeling

Computer Fundamentals

Presentation transcript:

IC TESTING

FUNDAMENTALS OF ELECTRICAL TESTING 1. What Is Electrical Testing? 2. Why Is Electrical Testing Necessary? 3. Anatomy of System-Level Electrical Testing 4. Fundamentals of Electrical Tests

WHAT IS ELECTRICAL TESTING? A systematic process involves testing at every step to guarantee the functionality and performance of the component before it is committed to the next step and ultimately to the final product.

Anatomy of electrical testing

WHY IS ELECTRICAL TESTING NECESSARY? When faulty chips pass an improperly designed test, they can cause system failures and enormous difficulty in system debugging. Debugging cost increases by about tenfold from chip level to board level, and also from board level to system level. Thus, it is of great importance to detect faults as early as possible.

COST OF TESTING All these combined make for a lot of testing and associated cost. This figure illustrates the product development cycle and approximate distribution of total cost. Design-for-test Test development Product testing These all testing phases can constitute as much as 45% of the total cost.

Fault Types and Models Physical Defects can cause Electrical and Logical Faults: Physical Defects include: Defects in silicon substrate Photolithographic defects Mask contamination and scratches Process variations and abnormalities Oxide defects

Electrical and Logical Faults Electrical Faults Logical Faults Shorts (bridging faults) Opens Transistors stuck-on, stuck-open Resistive shorts and opens Excessive change in threshold voltage Excessive steady-state currents Logical stuck-at-0 or stuck-at-1 Slower transition (delay faults) AND-bridging, OR-bridging

PHYSICAL DEFECT IN NOR2 FABRICATION

ELECTRICAL FAULT MODEL

LOGICAL FAULT MODEL

FUNDAMENTALS OF ELECTRICAL TESTS A system-under-test placed within a controlled environment that may include interactions and interfaces with other units. The response is one or more output electronic signals or simply a ‘‘pass/fail ’’indication. If the measured response matches the expected response (within an allowed margin of error) then the circuit ‘‘passes ’’the test.

Basic Concept of Electrical Tests

VIDEO OF CHIP TESTING

Test Pattern Generation and Fault Simulation

One possible SSF is characterized by the output of gate 1 being stuck-at logic zero (s-a-0).The fault is activated by applying a logic 1 at the inputs of gate 1. The only direct observation point is at the output of gate 4, the fault effect must be propagated through that gate. This is done by ‘‘sensitizing ’’a path through gate4, in this case by applying logic zeros to its other inputs. One way to accomplish that is to set (D,E,F,G) (0,0,1,0). So the input test pattern for this fault is (A,B,C,D,E,F,G) (1,0,1,0,0,1,0) and the OUTPUT 1 in the fault-free case, or OUTPUT 0 if the fault exists.

Thank you