Types of BJT Biasing Circuits By G.Kavitha ECE Dept Paavai Engineering College
Biasing Circuits of the BJT Normally, three types of circuits are used to establish dc biasing in a BJT, these are; (a) Fixed bias circuit (b) Collector-to-Base Bias Circuit (c) Voltage-Divider with Self-Bias Circuit (or) Self-Bias (or) Emitter Bias (or) Emitter-Stabilized Bias Circuit While designing the all four types of biasing circuits of BJT it is aimed to obtain Q-point parameters (IBQ, ICQ, VCEQ)
Fixed Bias
The Base-Emitter Loop From Kirchhoff’s voltage law: +VCC – IBRB – VBE = 0 Solving for base current:
Collector-Emitter Loop Collector current: From Kirchhoff’s voltage law:
Saturation When the transistor is operating in saturation, current through the transistor is at its maximum possible value.
The end points of the load line are: ICsat Load Line Analysis The end points of the load line are: ICsat IC = VCC / RC VCE = 0 V VCEcutoff VCE = VCC IC = 0 mA The Q-point is the operating point: where the value of RB sets the value of IB that sets the values of VCE and IC
Collector to Base Bias
Base-Emitter Loop From Kirchhoff’s voltage law: Where IB << IC: Knowing IC = IB and IE IC, the loop equation becomes: Solving for IB:
Collector-Emitter Loop From Kirchhoff’s voltage law: Since IC IC and IC = IB: Solving for VCE:
Voltage Divider Bias (or) Self Bias
Approximate Analysis Where IB << I1 and I1 I2 : Where bRE > 10R2: From Kirchhoff’s voltage law:
Voltage Divider Bias Analysis Transistor Saturation Level Load Line Analysis Cutoff: Saturation:
Emitter-Stabilized Bias Circuit
Base-Emitter Loop From Kirchhoff’s voltage law: Since IE = (b + 1)IB: Solving for IB:
Collector-Emitter Loop From Kirchhoff’s voltage law: Since IE IC: Also:
Improved Biased Stability Stability refers to a circuit condition in which the currents and voltages will remain fairly constant over a wide range of temperatures and transistor Beta () values. Adding RE to the emitter improves the stability of a transistor.
Saturation Level The endpoints can be determined from the load line. VCEcutoff: ICsat:
Emitter-Stabilized Bias Circuit
Base-Emitter Loop From Kirchhoff’s voltage law: Where IB << IC: Knowing IC = IB and IE IC, the loop equation becomes: Solving for IB:
Collector-Emitter Loop From Kirchhoff’s voltage law: Since IC IC and IC = IB: Solving for VCE:
Base-Emitter Bias Analysis Transistor Saturation Level Load Line Analysis Cutoff: Saturation:
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