Adders and Subtractors

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Presentation transcript:

Adders and Subtractors Discussion D4.1

Adders and Subtractors Carry and Overflow Subtractors Adder-Subtractor

Half Adder 1 1 +1 +1 2 10 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 Dec Binary A B S C 1 A B S C 1 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 Dec Binary 1 1 +1 +1 2 10

Multiple-bit Addition A3 A2 A1 A0 B3 B2 B1 B0 A 0 1 0 1 B 0 1 1 1 Ci+1 0 1 0 1 0 1 1 1 +Ci 1 1 1 A Ai +Bi B Si 1 1

Full Adder Si Ci Ai Bi Si Ci+1 Ci AiBi 00 01 11 10 1 0 0 0 0 0 1 Si 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1

Full Adder Ci Ai Bi Si Ci+1 Si = Ci'Ai'Bi + Ci'AiBi' + CiAi'Bi' 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1

Full Adder Si = Ci'Ai'Bi + Ci'AiBi' + CiAi'Bi' + CiAiBi Si = Ci'(Ai'Bi + AiBi') + Ci(Ai'Bi' + AiBi) Si = Ci'(Ai Bi) + Ci(Ai Bi)' Si = Ci (Ai Bi)

Full Adder Ci+1 Ci Ai Bi Si Ci+1 Ci AiBi 00 01 11 10 1 0 0 0 0 0 1 Ci+1 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1

Full Adder Ci+1 Ci AiBi 00 01 11 10 1 Ci Ai Bi Si Ci+1 0 0 0 0 0 1 Ci Ai Bi Si Ci+1 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 Ci+1 Ci+1 = AiBi + CiBi + CiAi

Full Adder Ci+1 Ci AiBi 00 01 11 10 1 Ci Ai Bi Si Ci+1 0 0 0 0 0 1 Ci Ai Bi Si Ci+1 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 Ci+1 Ci+1 = AiBi + CiAi'Bi + CiAiBi'

Full Adder Recall: Ci+1 = AiBi + CiAi'Bi + CiAiBi' Ci+1 = AiBi + Ci(Ai'Bi + AiBi') Ci+1 = AiBi + Ci(Ai Bi) Recall: Si = Ci (Ai Bi) Ci+1 = AiBi + Ci(Ai Bi)

Full Adder Si = Ci (Ai Bi) Ci+1 = AiBi + Ci(Ai Bi) Half-adder

Full Adder A full adder can be made from two half adders (plus an OR gate).

Full Adder Block Diagram

4-Bit Adder C 1 1 1 0 A 0 1 0 1 B 0 1 1 1 S 1 1 0 0

Full Adder Truth table Behavior Ci+1:Si = Ci + Ai + Bi Ci Si Ai Ci+1

Full Adder Block Diagram

4-Bit Adder C 1 1 1 0 0:A 0 1 1 0 1 0:B 0 0 1 1 1 C4:S 1 0 1 0 0

library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_unsigned.all; entity adder4 is port( A : in STD_LOGIC_VECTOR(3 downto 0); B : in STD_LOGIC_VECTOR(3 downto 0); carry : out STD_LOGIC; S : out STD_LOGIC_VECTOR(3 downto 0) ); end adder4; architecture adder4 of adder4 is begin process(A,B) variable temp: STD_LOGIC_VECTOR(4 downto 0); temp := ('0' & A) + ('0' & B); S <= temp(3 downto 0); carry <= temp(4); end process;

4-Bit Adder

Adders and Subtractors Carry and Overflow Subtractors Adder-Subtractor

Carry and Overflow 0 0 1 1 0 1 0 1 0 0 0 1 1 0 0 1 1 1 1 C = 0 V = 0 1 Binary 0 0 1 1 0 1 0 1 0 0 0 1 1 0 0 1 Dec 1 1 1 Hex 53 +25 78 35 +19 4E C = 0 V = 0 1 1 1 1 Note no carry from bit 6 to bit 7 and no carry from bit 7 to C.

Carry and Overflow Binary 0 0 1 1 0 1 0 1 0 1 0 1 1 0 1 1 1 1 1 1 1 1 1 Dec Hex 53 +91 144 35 +5B 90 C = 0 V = 1 1 1 Note carry from bit 6 to bit 7 but no carry from bit 7 to C. Thinking SIGNED we added two positive numbers and got a negative result. This can’t be correct! Therefore, the OVERFLOW bit, V, is set to 1. Correct answer (144) is outside the range -128 to +127.

Carry and Overflow Binary 0 0 1 1 0 1 0 1 1 1 0 1 0 0 1 1 1 1 1 1 1 1 Dec Hex 53 - 45 8 35 +D3 108 C = 1 V = 0 1 Ignore carry Note carry from bit 6 to bit 7 and carry from bit 7 to C. Thinking SIGNED we added a positive number to a negative number and got the correct positive answer. Therefore, the OVERFLOW bit, V, is cleared to 0. Correct answer (8) is inside the range -128 to +127.

Carry and Overflow 1 0 0 1 1 1 1 0 1 1 0 1 0 0 1 1 1 1 1 1 C = 1 V = 1 Binary 1 0 0 1 1 1 1 0 1 1 0 1 0 0 1 1 1 1 1 1 Dec Hex - 98 - 45 - 143 9E +D3 171 C = 1 V = 1 1 1 1 1 Ignore carry Note no carry from bit 6 to bit 7 but there is a carry from bit 7 to C. Thinking SIGNED we added two negative numbers and got a positive answer. This must be wrong! Therefore, the OVERFLOW bit, V, is set to 1. Correct answer (-143) is outside the range -128 to +127.

Overflow Note that the overflow bit was set whenever we had a carry from bit 6 to bit 7, but no carry from bit 7 to C. It was also set when we had a carry from bit 7 to C, but no carry from bit 6 to bit 7. Upshot: The overflow bit is the EXCLUSIVE-OR of a carry from bit 6 to bit 7 and a carry from bit 7 to C.

Adders and Subtractors Carry and Overflow Subtractors Adder-Subtractor

Half Subtractor 2 1 -1 1 0 0 0 0 0 1 1 1 1 0 1 0 1 1 0 0 A D B C A B D B D C 1 1 0 0 0 0 0 1 1 1 1 0 1 0 1 1 0 0 2 1 -1 1

Multiple-bit Subtraction A3 A2 A1 A0 B3 B2 B1 B0 A 0 1 0 1 B 0 1 1 1 Ci+1 0 1 0 1 0 1 1 1 - Ci 1 1 A Ai - Bi B Di 1 1 1 1

Full Subtractor Di Same as Si in full adder Ci Ai Bi Di Ci+1 Ci AiBi 00 01 11 10 1 0 0 0 0 0 0 0 1 1 1 0 1 0 1 0 0 1 1 0 0 1 0 0 1 1 1 0 1 0 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 Di Di = Ci (Ai Bi) Same as Si in full adder

Full Subtractor Ci+1 Ci AiBi 00 01 11 10 1 Ci Ai Bi Di Ci+1 0 0 0 0 0 1 Ci Ai Bi Di Ci+1 0 0 0 0 0 0 0 1 1 1 0 1 0 1 0 0 1 1 0 0 1 0 0 1 1 1 0 1 0 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 Ci+1 Ci+1 = Ai'Bi + CiAi'Bi' + CiAiBi

Full Subtractor Recall: Ci+1 = Ai'Bi + CiAi'Bi' + CiAiBi Ci+1 = Ai'Bi + Ci(Ai'Bi' + AiBi) Ci+1 = Ai'Bi + Ci(Ai Bi)' Recall: Di = Ci (Ai Bi) Ci+1 = Ai'Bi + Ci(Ai Bi)'

Full Subtractor half subtractor Di = Ci (Ai Bi) Ci+1 = Ai'Bi + Ci(Ai Bi)' half subtractor

Adders and Subtractors Carry and Overflow Subtractors Adder-Subtractor

Reordered Full Adder Full Subtractor Full Adder 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 1 1 1 0 1 0 1 0 0 1 1 0 0 1 0 0 1 1 1 0 1 0 1 1 1 0 0 0 1 1 1 1 1 Ci Ai Bi Di Ci+1 Full Subtractor Full Adder Ci Ai Bi Si Ci+1 Ci Ai Bi Si Ci+1 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 1 0 1 0 1 1 0 0 1 0 1 1 1 1 1 1 1 0 0 1 0 0 1 1 0 0 0 0 0 0 0 1 1 0 1 0 1 0 1 0 NOT

Making a full subtractor from a full adder

Adder/Subtractor E = 0: 4-bit adder E = 1: 4-bit subtractor

4-bit Subtractor: E = 1 +1 Add A to !B (one’s complement) plus 1 That is, add A to two’s complement of B D = A - B