9/15/09 - L23 More Sequential Circuits Copyright Joanne DeGroat, ECE, OSU1 More Sequential Circuits

9/15/09 - L23 More Sequential Circuits Copyright Joanne DeGroat, ECE, OSU2 Class 23-More Sequential Circuits  An up/down counter  A loadable down counter with signal  Material from section 5-5 of text

Design of and up/down counter  Problem Statement: Design a 3 bit binary clocked counter that counts up when the input C = 1 and counts down when the input C = 0. When the counter gets to 111 (000) it rolls over to 000 (111). 9/15/09 - L23 More Sequential Circuits Copyright Joanne DeGroat, ECE, OSU3

Problem Formulation  Will use a state table for this problem C=0 down C=1 up Present State Next State Next State /15/09 - L23 More Sequential Circuits Copyright Joanne DeGroat, ECE, OSU4

State Assignment  As this design involves a counter it already has binary values assigned to the states.  So we can move straight to creation of the next state generation.  The system will use D Flip-flops. 9/15/09 - L23 More Sequential Circuits Copyright Joanne DeGroat, ECE, OSU5

Next State Generation  In the table the Present State will be denoted by the 3-bit binary value as seen in the state table. The binary value is Q 2 Q 1 Q 0.  First the generation of Q 0. 9/15/09 - L23 More Sequential Circuits Copyright Joanne DeGroat, ECE, OSU6

Next State Generation D 1  Generate the next state equation for D 1 9/15/09 - L23 More Sequential Circuits Copyright Joanne DeGroat, ECE, OSU7

Next State Generation D 2  Generate the next state equation for D 2 9/15/09 - L23 More Sequential Circuits Copyright Joanne DeGroat, ECE, OSU8

Output Generation  Output generation is easy as it just the current state. 9/15/09 - L23 More Sequential Circuits Copyright Joanne DeGroat, ECE, OSU9

Verification via HDL  The models 9/15/09 - L23 More Sequential Circuits Copyright Joanne DeGroat, ECE, OSU10

The counter model  Uses the D FF 9/15/09 - L23 More Sequential Circuits Copyright Joanne DeGroat, ECE, OSU11

The Testbench  Need to apply stimulus and look at results. 9/15/09 - L23 More Sequential Circuits Copyright Joanne DeGroat, ECE, OSU12

Simultion Results  The waveform for counting up 9/15/09 - L23 More Sequential Circuits Copyright Joanne DeGroat, ECE, OSU13

Simultion Results  The waveform for counting down 9/15/09 - L23 More Sequential Circuits Copyright Joanne DeGroat, ECE, OSU14

Simulation Results  Waveform for up again and back to down 9/15/09 - L23 More Sequential Circuits Copyright Joanne DeGroat, ECE, OSU15

Changing format to octal display  For a more readable output 9/15/09 - L23 More Sequential Circuits Copyright Joanne DeGroat, ECE, OSU16

A Loadable countdown timer  Specification: Design a loadable 3-bit countdown timer the after loading counts down to 0 and then generates a signal Z which will stay asserted as long as the countdown is enabled.  When the counter reaches 0 it remains there until a new count is loaded. 9/15/09 - L23 More Sequential Circuits Copyright Joanne DeGroat, ECE, OSU17

The state table  The state table showing both count enable and load 9/15/09 - L23 More Sequential Circuits Copyright Joanne DeGroat, ECE, OSU18

K-maps  The K-maps for the circuit are. 9/15/09 - L23 More Sequential Circuits Copyright Joanne DeGroat, ECE, OSU19

The output  The output signal Z is asserted when state 000 is reached. It stays asserted as long as C is asserted. 9/15/09 - L23 More Sequential Circuits Copyright Joanne DeGroat, ECE, OSU20

The circuit  Has 3 FFs 9/15/09 - L23 More Sequential Circuits Copyright Joanne DeGroat, ECE, OSU21

Class 23 assignment  Covered sections 5-5  Problems for hand in Nothing new  Problems for practice Nothing new  Reading for next class: 5-6 9/15/09 - L23 More Sequential Circuits Copyright Joanne DeGroat, ECE, OSU22