Slide title 70 pt CAPITALS Slide subtitle minimum 30 pt cheap silicon: myth or reality? Picking the right data plane hardware for software defined networking Gergely Pongrácz, László Molnár, Zoltán Lajos Kis, Zoltán Turányi TrafficLab, Ericsson Research, Budapest, Hungary

Slide title 44 pt Text and bullet level 1 minimum 24 pt Bullets level 2-5 minimum 20 pt Characters for Embedded font: !"#$%&'()*+,-./ :; WXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~¡ ¢£¤¥¦§¨©ª«¬®¯°±²³´¶·¸¹º»¼½ÀÁÂÃÄÅÆÇÈËÌÍÎÏÐÑÒ ÓÔÕÖ×ØÙÚÛÜÝÞßàáâãäåæçèéêëìíîïðñòóôõö ÷øùúûüýþÿĀāĂăąĆćĊċČĎďĐđĒĖėĘęĚěĞğĠġĢģ ĪīĮįİıĶķĹĺĻļĽľŁłŃńŅņŇňŌŐőŒœŔŕŖŗŘřŚśŞşŠšŢ ţŤťŪūŮůŰűŲųŴŵŶŷŸŹźŻżŽžƒȘșˆˇ˘˙˚˛˜˝ẀẁẃẄẅ Ỳỳ–— ‘’‚“”„†‡…‰‹›⁄€™ĀĀĂĂĄĄĆĆĊĊČČĎĎĐĐĒĒĖĖĘĘĚĚĞĞ ĠĠĢĢĪĪĮĮİĶĶĹĹĻĻĽĽŃŃŅŅŇŇŌŌŐŐŔŔŖŖŘŘŚŚŞŞŢŢŤ ŤŪŪŮŮŰŰŲŲŴŴŶŶŹŹŻŻȘș−≤≥fifl ΆΈΉΊΌΎΏΐΑΒΓΕΖΗΘΙΚΛΜΝΞΟΠΡΣΤΥΦΧΨΪΫΆΈΉΊΰ αβγδεζηθικλνξορςΣΤΥΦΧΨΩΪΫΌΎΏ ЁЂЃЄЅІЇЈЉЊЋЌЎЏАБВГДЕЖЗИЙКЛМНОПРСТУФХ ЦЧШЩЪЫЬЭЮЯАБВГДЕЖЗИЙКЛМНОПРСТУФХЦ ЧШЩЪЫЬЭЮЯЁЂЃЄЅІЇЈЉЊЋЌЎЏѢѢѲѲѴѴҐҐә ǽ Ẁ ẁẂẃẄẅỲỳ№ Do not add objects or text in the footer area Page 2 DP CHIP landscape the usual way of thinking SNP, Netronome NP4 Fulcrum Broadcom/Marvel Programmability performance Assuming same use case and table sizes The main question that is seldom asked: How big is the difference? Fixed pipeline (higher performance) Programmable pipeline Generic NP run-to-completion (lower performance)

Slide title 44 pt Text and bullet level 1 minimum 24 pt Bullets level 2-5 minimum 20 pt Characters for Embedded font: !"#$%&'()*+,-./ :; WXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~¡ ¢£¤¥¦§¨©ª«¬®¯°±²³´¶·¸¹º»¼½ÀÁÂÃÄÅÆÇÈËÌÍÎÏÐÑÒ ÓÔÕÖ×ØÙÚÛÜÝÞßàáâãäåæçèéêëìíîïðñòóôõö ÷øùúûüýþÿĀāĂăąĆćĊċČĎďĐđĒĖėĘęĚěĞğĠġĢģ ĪīĮįİıĶķĹĺĻļĽľŁłŃńŅņŇňŌŐőŒœŔŕŖŗŘřŚśŞşŠšŢ ţŤťŪūŮůŰűŲųŴŵŶŷŸŹźŻżŽžƒȘșˆˇ˘˙˚˛˜˝ẀẁẃẄẅ Ỳỳ–— ‘’‚“”„†‡…‰‹›⁄€™ĀĀĂĂĄĄĆĆĊĊČČĎĎĐĐĒĒĖĖĘĘĚĚĞĞ ĠĠĢĢĪĪĮĮİĶĶĹĹĻĻĽĽŃŃŅŅŇŇŌŌŐŐŔŔŖŖŘŘŚŚŞŞŢŢŤ ŤŪŪŮŮŰŰŲŲŴŴŶŶŹŹŻŻȘș−≤≥fifl ΆΈΉΊΌΎΏΐΑΒΓΕΖΗΘΙΚΛΜΝΞΟΠΡΣΤΥΦΧΨΪΫΆΈΉΊΰ αβγδεζηθικλνξορςΣΤΥΦΧΨΩΪΫΌΎΏ ЁЂЃЄЅІЇЈЉЊЋЌЎЏАБВГДЕЖЗИЙКЛМНОПРСТУФХ ЦЧШЩЪЫЬЭЮЯАБВГДЕЖЗИЙКЛМНОПРСТУФХЦ ЧШЩЪЫЬЭЮЯЁЂЃЄЅІЇЈЉЊЋЌЎЏѢѢѲѲѴѴҐҐә ǽ Ẁ ẁẂẃẄẅỲỳ№ Do not add objects or text in the footer area Page 3 Chip name (nm)GbpsMpps Power / 10G Type Ericsson SNP 4000 (45) WNPU Netronome NFP-6 (22) WNPU Cavium Octeon III (28)100?5WNPU Tilera Gx8036 (40) WNPU Intel X-E DPDK (32)508024WCPU EzChip NP4 (55) WPP Marvell Xelerated AX (65)100150?PP EzChip NP5 (28)200?3WPP Intel FM6372 (65) WSwitch BCM56840 (40)640??Switch Marvell Lion 2 (40) WSwitch first comparison NPUs ~4-5 W / 10G CPUs ~25 W / 10G Prog. pipelines ~3-4 W / 10G Switches ~0.5 W / 10G So it seems there is a 5-10x difference between “cheap silicon” and programmable devices But do we compare apples to apples?

Slide title 70 pt CAPITALS Slide subtitle minimum 30 pt the PBB scenario - modelling summary -

Slide title 44 pt Text and bullet level 1 minimum 24 pt Bullets level 2-5 minimum 20 pt Characters for Embedded font: !"#$%&'()*+,-./ :; WXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~¡ ¢£¤¥¦§¨©ª«¬®¯°±²³´¶·¸¹º»¼½ÀÁÂÃÄÅÆÇÈËÌÍÎÏÐÑÒ ÓÔÕÖ×ØÙÚÛÜÝÞßàáâãäåæçèéêëìíîïðñòóôõö ÷øùúûüýþÿĀāĂăąĆćĊċČĎďĐđĒĖėĘęĚěĞğĠġĢģ ĪīĮįİıĶķĹĺĻļĽľŁłŃńŅņŇňŌŐőŒœŔŕŖŗŘřŚśŞşŠšŢ ţŤťŪūŮůŰűŲųŴŵŶŷŸŹźŻżŽžƒȘșˆˇ˘˙˚˛˜˝ẀẁẃẄẅ Ỳỳ–— ‘’‚“”„†‡…‰‹›⁄€™ĀĀĂĂĄĄĆĆĊĊČČĎĎĐĐĒĒĖĖĘĘĚĚĞĞ ĠĠĢĢĪĪĮĮİĶĶĹĹĻĻĽĽŃŃŅŅŇŇŌŌŐŐŔŔŖŖŘŘŚŚŞŞŢŢŤ ŤŪŪŮŮŰŰŲŲŴŴŶŶŹŹŻŻȘș−≤≥fifl ΆΈΉΊΌΎΏΐΑΒΓΕΖΗΘΙΚΛΜΝΞΟΠΡΣΤΥΦΧΨΪΫΆΈΉΊΰ αβγδεζηθικλνξορςΣΤΥΦΧΨΩΪΫΌΎΏ ЁЂЃЄЅІЇЈЉЊЋЌЎЏАБВГДЕЖЗИЙКЛМНОПРСТУФХ ЦЧШЩЪЫЬЭЮЯАБВГДЕЖЗИЙКЛМНОПРСТУФХЦ ЧШЩЪЫЬЭЮЯЁЂЃЄЅІЇЈЉЊЋЌЎЏѢѢѲѲѴѴҐҐә ǽ Ẁ ẁẂẃẄẅỲỳ№ Do not add objects or text in the footer area Page 5 Simple NP/CPU model Internal bus Processing unit(s) (e.g., pipeline, execution unit) Accelerators (e.g., RE engines, TCAM, hw queue, encyption) On-Chip memory (e.g., cache, scratchpad) Ethernet (e.g, 10G, 40G) Fabric (e.g, Interlaken) System (e.g, PCIe) External Resource Control (e.g., optional TCAM, external memory) External memory (e.g, DDR3) Optional accelerators (e.g, TCAM) I/O

Slide title 44 pt Text and bullet level 1 minimum 24 pt Bullets level 2-5 minimum 20 pt Characters for Embedded font: !"#$%&'()*+,-./ :; WXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~¡ ¢£¤¥¦§¨©ª«¬®¯°±²³´¶·¸¹º»¼½ÀÁÂÃÄÅÆÇÈËÌÍÎÏÐÑÒ ÓÔÕÖ×ØÙÚÛÜÝÞßàáâãäåæçèéêëìíîïðñòóôõö ÷øùúûüýþÿĀāĂăąĆćĊċČĎďĐđĒĖėĘęĚěĞğĠġĢģ ĪīĮįİıĶķĹĺĻļĽľŁłŃńŅņŇňŌŐőŒœŔŕŖŗŘřŚśŞşŠšŢ ţŤťŪūŮůŰűŲųŴŵŶŷŸŹźŻżŽžƒȘșˆˇ˘˙˚˛˜˝ẀẁẃẄẅ Ỳỳ–— ‘’‚“”„†‡…‰‹›⁄€™ĀĀĂĂĄĄĆĆĊĊČČĎĎĐĐĒĒĖĖĘĘĚĚĞĞ ĠĠĢĢĪĪĮĮİĶĶĹĹĻĻĽĽŃŃŅŅŇŇŌŌŐŐŔŔŖŖŘŘŚŚŞŞŢŢŤ ŤŪŪŮŮŰŰŲŲŴŴŶŶŹŹŻŻȘș−≤≥fifl ΆΈΉΊΌΎΏΐΑΒΓΕΖΗΘΙΚΛΜΝΞΟΠΡΣΤΥΦΧΨΪΫΆΈΉΊΰ αβγδεζηθικλνξορςΣΤΥΦΧΨΩΪΫΌΎΏ ЁЂЃЄЅІЇЈЉЊЋЌЎЏАБВГДЕЖЗИЙКЛМНОПРСТУФХ ЦЧШЩЪЫЬЭЮЯАБВГДЕЖЗИЙКЛМНОПРСТУФХЦ ЧШЩЪЫЬЭЮЯЁЂЃЄЅІЇЈЉЊЋЌЎЏѢѢѲѲѴѴҐҐә ǽ Ẁ ẁẂẃẄẅỲỳ№ Do not add objects or text in the footer area Page 6 Internal bus GHz None L1 SRAM 4B/clock per core >128B External port Fabric System 8 MCT 340 Mtps >1 GB High capacity memory (e.g, DDR3) Low latency RAM (e.g, RLDRAM) 96x10G L2 eDRAM 24 Gtps shared >2 MB

Slide title 44 pt Text and bullet level 1 minimum 24 pt Bullets level 2-5 minimum 20 pt Characters for Embedded font: !"#$%&'()*+,-./ :; WXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~¡ ¢£¤¥¦§¨©ª«¬®¯°±²³´¶·¸¹º»¼½ÀÁÂÃÄÅÆÇÈËÌÍÎÏÐÑÒ ÓÔÕÖ×ØÙÚÛÜÝÞßàáâãäåæçèéêëìíîïðñòóôõö ÷øùúûüýþÿĀāĂăąĆćĊċČĎďĐđĒĖėĘęĚěĞğĠġĢģ ĪīĮįİıĶķĹĺĻļĽľŁłŃńŅņŇňŌŐőŒœŔŕŖŗŘřŚśŞşŠšŢ ţŤťŪūŮůŰűŲųŴŵŶŷŸŹźŻżŽžƒȘșˆˇ˘˙˚˛˜˝ẀẁẃẄẅ Ỳỳ–— ‘’‚“”„†‡…‰‹›⁄€™ĀĀĂĂĄĄĆĆĊĊČČĎĎĐĐĒĒĖĖĘĘĚĚĞĞ ĠĠĢĢĪĪĮĮİĶĶĹĹĻĻĽĽŃŃŅŅŇŇŌŌŐŐŔŔŖŖŘŘŚŚŞŞŢŢŤ ŤŪŪŮŮŰŰŲŲŴŴŶŶŹŹŻŻȘș−≤≥fifl ΆΈΉΊΌΎΏΐΑΒΓΕΖΗΘΙΚΛΜΝΞΟΠΡΣΤΥΦΧΨΪΫΆΈΉΊΰ αβγδεζηθικλνξορςΣΤΥΦΧΨΩΪΫΌΎΏ ЁЂЃЄЅІЇЈЉЊЋЌЎЏАБВГДЕЖЗИЙКЛМНОПРСТУФХ ЦЧШЩЪЫЬЭЮЯАБВГДЕЖЗИЙКЛМНОПРСТУФХЦ ЧШЩЪЫЬЭЮЯЁЂЃЄЅІЇЈЉЊЋЌЎЏѢѢѲѲѴѴҐҐә ǽ Ẁ ẁẂẃẄẅỲỳ№ Do not add objects or text in the footer area Page 7 1.read frame from I/O: copy to L2 memory, copy header to L1 memory 2.parse fixed header fields 3.find extended VLAN {sport, S-VID  eVLAN}: table in L2 memory 4.MAC lookup and learning {eVLAN, C-DMAC  B-DMAC, dport, flags}: table in ext. memory 5.encapsulate: create new header, fill in values (no further lookup) 6.send frame to I/O packet walkthrough

Slide title 44 pt Text and bullet level 1 minimum 24 pt Bullets level 2-5 minimum 20 pt Characters for Embedded font: !"#$%&'()*+,-./ :; WXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~¡ ¢£¤¥¦§¨©ª«¬®¯°±²³´¶·¸¹º»¼½ÀÁÂÃÄÅÆÇÈËÌÍÎÏÐÑÒ ÓÔÕÖ×ØÙÚÛÜÝÞßàáâãäåæçèéêëìíîïðñòóôõö ÷øùúûüýþÿĀāĂăąĆćĊċČĎďĐđĒĖėĘęĚěĞğĠġĢģ ĪīĮįİıĶķĹĺĻļĽľŁłŃńŅņŇňŌŐőŒœŔŕŖŗŘřŚśŞşŠšŢ ţŤťŪūŮůŰűŲųŴŵŶŷŸŹźŻżŽžƒȘșˆˇ˘˙˚˛˜˝ẀẁẃẄẅ Ỳỳ–— ‘’‚“”„†‡…‰‹›⁄€™ĀĀĂĂĄĄĆĆĊĊČČĎĎĐĐĒĒĖĖĘĘĚĚĞĞ ĠĠĢĢĪĪĮĮİĶĶĹĹĻĻĽĽŃŃŅŅŇŇŌŌŐŐŔŔŖŖŘŘŚŚŞŞŢŢŤ ŤŪŪŮŮŰŰŲŲŴŴŶŶŹŹŻŻȘș−≤≥fifl ΆΈΉΊΌΎΏΐΑΒΓΕΖΗΘΙΚΛΜΝΞΟΠΡΣΤΥΦΧΨΪΫΆΈΉΊΰ αβγδεζηθικλνξορςΣΤΥΦΧΨΩΪΫΌΎΏ ЁЂЃЄЅІЇЈЉЊЋЌЎЏАБВГДЕЖЗИЙКЛМНОПРСТУФХ ЦЧШЩЪЫЬЭЮЯАБВГДЕЖЗИЙКЛМНОПРСТУФХЦ ЧШЩЪЫЬЭЮЯЁЂЃЄЅІЇЈЉЊЋЌЎЏѢѢѲѲѴѴҐҐә ǽ Ẁ ẁẂẃẄẅỲỳ№ Do not add objects or text in the footer area Page 8 ›Don’t worry, no time for this –but the code pieces can be found in the paper assembly code

Slide title 44 pt Text and bullet level 1 minimum 24 pt Bullets level 2-5 minimum 20 pt Characters for Embedded font: !"#$%&'()*+,-./ :; WXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~¡ ¢£¤¥¦§¨©ª«¬®¯°±²³´¶·¸¹º»¼½ÀÁÂÃÄÅÆÇÈËÌÍÎÏÐÑÒ ÓÔÕÖ×ØÙÚÛÜÝÞßàáâãäåæçèéêëìíîïðñòóôõö ÷øùúûüýþÿĀāĂăąĆćĊċČĎďĐđĒĖėĘęĚěĞğĠġĢģ ĪīĮįİıĶķĹĺĻļĽľŁłŃńŅņŇňŌŐőŒœŔŕŖŗŘřŚśŞşŠšŢ ţŤťŪūŮůŰűŲųŴŵŶŷŸŹźŻżŽžƒȘșˆˇ˘˙˚˛˜˝ẀẁẃẄẅ Ỳỳ–— ‘’‚“”„†‡…‰‹›⁄€™ĀĀĂĂĄĄĆĆĊĊČČĎĎĐĐĒĒĖĖĘĘĚĚĞĞ ĠĠĢĢĪĪĮĮİĶĶĹĹĻĻĽĽŃŃŅŅŇŇŌŌŐŐŔŔŖŖŘŘŚŚŞŞŢŢŤ ŤŪŪŮŮŰŰŲŲŴŴŶŶŹŹŻŻȘș−≤≥fifl ΆΈΉΊΌΎΏΐΑΒΓΕΖΗΘΙΚΛΜΝΞΟΠΡΣΤΥΦΧΨΪΫΆΈΉΊΰ αβγδεζηθικλνξορςΣΤΥΦΧΨΩΪΫΌΎΏ ЁЂЃЄЅІЇЈЉЊЋЌЎЏАБВГДЕЖЗИЙКЛМНОПРСТУФХ ЦЧШЩЪЫЬЭЮЯАБВГДЕЖЗИЙКЛМНОПРСТУФХЦ ЧШЩЪЫЬЭЮЯЁЂЃЄЅІЇЈЉЊЋЌЎЏѢѢѲѲѴѴҐҐә ǽ Ẁ ẁẂẃẄẅỲỳ№ Do not add objects or text in the footer area Page 9 ›PBB processing in average –104 clock cycles –25 L2 operations (depends on packet size) –1 external RAM operation ›Calculated performance (pps) –packet size = 750B  960 Mpps = 5760 Gbps ›cores + L1 memory: 2462 Mpps ›L2 memory: 960 Mpps ›ext. memory: 2720 Mpps –packet size = 64B  bottleneck moves to cores  2462 Mpps = 1260 Gbps pps/bw calculation only summary* * assembly code and detailed calculation is available in the paper

Slide title 44 pt Text and bullet level 1 minimum 24 pt Bullets level 2-5 minimum 20 pt Characters for Embedded font: !"#$%&'()*+,-./ :; WXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~¡ ¢£¤¥¦§¨©ª«¬®¯°±²³´¶·¸¹º»¼½ÀÁÂÃÄÅÆÇÈËÌÍÎÏÐÑÒ ÓÔÕÖ×ØÙÚÛÜÝÞßàáâãäåæçèéêëìíîïðñòóôõö ÷øùúûüýþÿĀāĂăąĆćĊċČĎďĐđĒĖėĘęĚěĞğĠġĢģ ĪīĮįİıĶķĹĺĻļĽľŁłŃńŅņŇňŌŐőŒœŔŕŖŗŘřŚśŞşŠšŢ ţŤťŪūŮůŰűŲųŴŵŶŷŸŹźŻżŽžƒȘșˆˇ˘˙˚˛˜˝ẀẁẃẄẅ Ỳỳ–— ‘’‚“”„†‡…‰‹›⁄€™ĀĀĂĂĄĄĆĆĊĊČČĎĎĐĐĒĒĖĖĘĘĚĚĞĞ ĠĠĢĢĪĪĮĮİĶĶĹĹĻĻĽĽŃŃŅŅŇŇŌŌŐŐŔŔŖŖŘŘŚŚŞŞŢŢŤ ŤŪŪŮŮŰŰŲŲŴŴŶŶŹŹŻŻȘș−≤≥fifl ΆΈΉΊΌΎΏΐΑΒΓΕΖΗΘΙΚΛΜΝΞΟΠΡΣΤΥΦΧΨΪΫΆΈΉΊΰ αβγδεζηθικλνξορςΣΤΥΦΧΨΩΪΫΌΎΏ ЁЂЃЄЅІЇЈЉЊЋЌЎЏАБВГДЕЖЗИЙКЛМНОПРСТУФХ ЦЧШЩЪЫЬЭЮЯАБВГДЕЖЗИЙКЛМНОПРСТУФХЦ ЧШЩЪЫЬЭЮЯЁЂЃЄЅІЇЈЉЊЋЌЎЏѢѢѲѲѴѴҐҐә ǽ Ẁ ẁẂẃẄẅỲỳ№ Do not add objects or text in the footer area Page 10 Ethernet PBB scenario overview of results Chip namePowerMpps Mpps / Watt Type Ericsson SNP W NPU Netronome NFP-650W4939.9NPU Cavium Octeon III50W4809.6NPU Tilera Gx803625W1807.2NPU Intel X-E DPDK120W1181CPU EzChip NP435W3339.5PP Intel FM637280W Switch Marvell Lion 245W72016Switch ›Results are theoretical: programmable chips today are designed for more complex tasks with less I/O ports vs Mpps / Watt: 20-30% advantage: around 1.25x instead of 10x

Slide title 70 pt CAPITALS Slide subtitle minimum 30 pt summary and next steps I’d have to make it really fast if I spent >8 minutes so far

Slide title 44 pt Text and bullet level 1 minimum 24 pt Bullets level 2-5 minimum 20 pt Characters for Embedded font: !"#$%&'()*+,-./ :; WXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~¡ ¢£¤¥¦§¨©ª«¬®¯°±²³´¶·¸¹º»¼½ÀÁÂÃÄÅÆÇÈËÌÍÎÏÐÑÒ ÓÔÕÖ×ØÙÚÛÜÝÞßàáâãäåæçèéêëìíîïðñòóôõö ÷øùúûüýþÿĀāĂăąĆćĊċČĎďĐđĒĖėĘęĚěĞğĠġĢģ ĪīĮįİıĶķĹĺĻļĽľŁłŃńŅņŇňŌŐőŒœŔŕŖŗŘřŚśŞşŠšŢ ţŤťŪūŮůŰűŲųŴŵŶŷŸŹźŻżŽžƒȘșˆˇ˘˙˚˛˜˝ẀẁẃẄẅ Ỳỳ–— ‘’‚“”„†‡…‰‹›⁄€™ĀĀĂĂĄĄĆĆĊĊČČĎĎĐĐĒĒĖĖĘĘĚĚĞĞ ĠĠĢĢĪĪĮĮİĶĶĹĹĻĻĽĽŃŃŅŅŇŇŌŌŐŐŔŔŖŖŘŘŚŚŞŞŢŢŤ ŤŪŪŮŮŰŰŲŲŴŴŶŶŹŹŻŻȘș−≤≥fifl ΆΈΉΊΌΎΏΐΑΒΓΕΖΗΘΙΚΛΜΝΞΟΠΡΣΤΥΦΧΨΪΫΆΈΉΊΰ αβγδεζηθικλνξορςΣΤΥΦΧΨΩΪΫΌΎΏ ЁЂЃЄЅІЇЈЉЊЋЌЎЏАБВГДЕЖЗИЙКЛМНОПРСТУФХ ЦЧШЩЪЫЬЭЮЯАБВГДЕЖЗИЙКЛМНОПРСТУФХЦ ЧШЩЪЫЬЭЮЯЁЂЃЄЅІЇЈЉЊЋЌЎЏѢѢѲѲѴѴҐҐә ǽ Ẁ ẁẂẃẄẅỲỳ№ Do not add objects or text in the footer area Page 12 ›Performance depends mainly on the use case, not on the selected hardware solution –not valid for Intel-like generic CPU – much lower perf. at simple use cases ›but even this might change with manycore Intel products (e.g. Xeon Phi) –on a board/card level local processor also counts – known problem for NP4 ›Future memory technologies (e.g. HMC, HBM, 3D) might change the picture again –much higher transaction rate, low power consumption what we’ve learned so far…

Slide title 44 pt Text and bullet level 1 minimum 24 pt Bullets level 2-5 minimum 20 pt Characters for Embedded font: !"#$%&'()*+,-./ :; WXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~¡ ¢£¤¥¦§¨©ª«¬®¯°±²³´¶·¸¹º»¼½ÀÁÂÃÄÅÆÇÈËÌÍÎÏÐÑÒ ÓÔÕÖ×ØÙÚÛÜÝÞßàáâãäåæçèéêëìíîïðñòóôõö ÷øùúûüýþÿĀāĂăąĆćĊċČĎďĐđĒĖėĘęĚěĞğĠġĢģ ĪīĮįİıĶķĹĺĻļĽľŁłŃńŅņŇňŌŐőŒœŔŕŖŗŘřŚśŞşŠšŢ ţŤťŪūŮůŰűŲųŴŵŶŷŸŹźŻżŽžƒȘșˆˇ˘˙˚˛˜˝ẀẁẃẄẅ Ỳỳ–— ‘’‚“”„†‡…‰‹›⁄€™ĀĀĂĂĄĄĆĆĊĊČČĎĎĐĐĒĒĖĖĘĘĚĚĞĞ ĠĠĢĢĪĪĮĮİĶĶĹĹĻĻĽĽŃŃŅŅŇŇŌŌŐŐŔŔŖŖŘŘŚŚŞŞŢŢŤ ŤŪŪŮŮŰŰŲŲŴŴŶŶŹŹŻŻȘș−≤≥fifl ΆΈΉΊΌΎΏΐΑΒΓΕΖΗΘΙΚΛΜΝΞΟΠΡΣΤΥΦΧΨΪΫΆΈΉΊΰ αβγδεζηθικλνξορςΣΤΥΦΧΨΩΪΫΌΎΏ ЁЂЃЄЅІЇЈЉЊЋЌЎЏАБВГДЕЖЗИЙКЛМНОПРСТУФХ ЦЧШЩЪЫЬЭЮЯАБВГДЕЖЗИЙКЛМНОПРСТУФХЦ ЧШЩЪЫЬЭЮЯЁЂЃЄЅІЇЈЉЊЋЌЎЏѢѢѲѲѴѴҐҐә ǽ Ẁ ẁẂẃẄẅỲỳ№ Do not add objects or text in the footer area Page 13 ›So far it seems that a programmable NPU would be suitable for all tasks ›BUT! For which use case shall we balance the I/O and the processing complex? –today we have a (mostly) static I/O built together with the NPU –we do have >10x packet processing performance difference between important use cases ›How to solve it? ›Different NPU – I/O flavors: still quite static solution –but an (almost) always oversubscribed I/O could do the job ›I/O – forwarding separation: modular HW But! – no free lunch the hard part: I/O balance

Slide title 44 pt Text and bullet level 1 minimum 24 pt Bullets level 2-5 minimum 20 pt Characters for Embedded font: !"#$%&'()*+,-./ :; WXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~¡ ¢£¤¥¦§¨©ª«¬®¯°±²³´¶·¸¹º»¼½ÀÁÂÃÄÅÆÇÈËÌÍÎÏÐÑÒ ÓÔÕÖ×ØÙÚÛÜÝÞßàáâãäåæçèéêëìíîïðñòóôõö ÷øùúûüýþÿĀāĂăąĆćĊċČĎďĐđĒĖėĘęĚěĞğĠġĢģ ĪīĮįİıĶķĹĺĻļĽľŁłŃńŅņŇňŌŐőŒœŔŕŖŗŘřŚśŞşŠšŢ ţŤťŪūŮůŰűŲųŴŵŶŷŸŹźŻżŽžƒȘșˆˇ˘˙˚˛˜˝ẀẁẃẄẅ Ỳỳ–— ‘’‚“”„†‡…‰‹›⁄€™ĀĀĂĂĄĄĆĆĊĊČČĎĎĐĐĒĒĖĖĘĘĚĚĞĞ ĠĠĢĢĪĪĮĮİĶĶĹĹĻĻĽĽŃŃŅŅŇŇŌŌŐŐŔŔŖŖŘŘŚŚŞŞŢŢŤ ŤŪŪŮŮŰŰŲŲŴŴŶŶŹŹŻŻȘș−≤≥fifl ΆΈΉΊΌΎΏΐΑΒΓΕΖΗΘΙΚΛΜΝΞΟΠΡΣΤΥΦΧΨΪΫΆΈΉΊΰ αβγδεζηθικλνξορςΣΤΥΦΧΨΩΪΫΌΎΏ ЁЂЃЄЅІЇЈЉЊЋЌЎЏАБВГДЕЖЗИЙКЛМНОПРСТУФХ ЦЧШЩЪЫЬЭЮЯАБВГДЕЖЗИЙКЛМНОПРСТУФХЦ ЧШЩЪЫЬЭЮЯЁЂЃЄЅІЇЈЉЊЋЌЎЏѢѢѲѲѴѴҐҐә ǽ Ẁ ẁẂẃẄẅỲỳ№ Do not add objects or text in the footer area Page 14 ›Prove by prototyping –use ongoing OpenFlow prototyping activity –OF switch can be configured to act as PBB –SNP hardware will be available in our lab at 2013 Q4 –Intel (DPDK) version is ready, first results will be EWSDN 13 ›Evaluate the model and make it more accurate –more accurate memory and processor models ›e.g. calculate with utilization based power consumption –identify possible other bottlenecks ›e.g. backplane, on-chip network what is next ongoing and planned activities

Slide title 70 pt CAPITALS Slide subtitle minimum 30 pt thank you! And let’s discuss these further