The Synthesis of Cyclic Circuits with SAT and Interpolation By John Backes and Marc Riedel ECE University of Minnesota.

Slides:



Advertisements
Similar presentations
FRAIGs - A Unifying Representation for Logic Synthesis and Verification - Alan Mishchenko, Satrajit Chatterjee, Roland Jiang, Robert Brayton ERL Technical.
Advertisements

Representing Boolean Functions for Symbolic Model Checking Supratik Chakraborty IIT Bombay.
Aaron Bradley University of Colorado, Boulder
The Analysis of Cyclic Circuits with Boolean Satisfiability John Backes, Brian Fett, and Marc Riedel Electrical Engineering, University of Minnesota.
Reduction of Interpolants for Logic Synthesis John Backes Marc Riedel University of Minnesota Dept.
Algorithms and Data Structures for Logic Synthesis and Verification using Boolean Satisfiability John Backes Advisor: Marc Riedel
ECE 667 Synthesis & Verification - SAT 1 ECE 667 ECE 667 Synthesis and Verification of Digital Systems Boolean SAT CNF Representation Slides adopted (with.
ECE Synthesis & Verification1 ECE 667 Spring 2011 Synthesis and Verification of Digital Systems Verification Introduction.
Cyclic Combinational Circuits Theory Marc D. Riedel California Institute of Technology Marrella splendensCyclic circuit (500 million year old Trilobite)(novel.
Bounded Model Checking EECS 290A Sequential Logic Synthesis and Verification.
EE290A 1 Retiming of AND- INVERTER graphs with latches Juliet Holwill 290A Project 10 May 2005.
1 FRAIGs: Functionally Reduced And-Inverter Graphs Adapted from the paper “FRAIGs: A Unifying Representation for Logic Synthesis and Verification”, by.
DAG-Aware AIG Rewriting Alan Mishchenko, Satrajit Chatterjee, Robert Brayton Department of EECS, University of California Berkeley Presented by Rozana.
Timing Analysis of Cyclic Combinational Circuits Marc D. Riedel and Jehoshua Bruck California Institute of Technology IWLS, Temecula Creek, CA, June 4,
01/27/2005 Combinationality of cyclic definitions EECS 290A – Spring 2005 UC Berkeley.
ECE Synthesis & Verification, Lecture 17 1 ECE 697B (667) Spring 2006 ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Systems Technology.
USING SAT-BASED CRAIG INTERPOLATION TO ENLARGE CLOCK GATING FUNCTIONS Ting-Hao Lin, Chung-Yang (Ric) Huang Graduate Institute of Electrical Engineering,
Property Directed Reachability (PDR) Using Cubes of Non-state Variables With Property Directed Reachability Using Cubes of Non-state Variables With Property.
Lazy Annotation for Program Testing and Verification Speaker: Chen-Hsuan Adonis Lin Advisor: Jie-Hong Roland Jiang November 26,
On the Relation between SAT and BDDs for Equivalence Checking Sherief Reda Rolf Drechsler Alex Orailoglu Computer Science & Engineering Dept. University.
Cut-Based Inductive Invariant Computation Michael Case 1,2 Alan Mishchenko 1 Robert Brayton 1 Robert Brayton 1 1 UC Berkeley 2 IBM Systems and Technology.
Boolean Satisfiability Present and Future
Courtesy RK Brayton (UCB) and A Kuehlmann (Cadence) 1 Logic Synthesis Multi-Level Logic Synthesis.
2009/2/10NTUEE Research Projects1 Applied Logic & Computation in System Design - A Research Invitation Jie-Hong R. Jiang 江介宏 NTUEE/GIEE National Taiwan.
Research Roadmap Past – Present – Future Robert Brayton Alan Mishchenko Logic Synthesis and Verification Group UC Berkeley.
1 Alan Mishchenko Research Update June-September 2008.
2009/6/30 CAV Quantifier Elimination via Functional Composition Jie-Hong Roland Jiang Dept. of Electrical Eng. / Grad. Inst. of Electronics Eng.
A Semi-Canonical Form for Sequential Circuits Alan Mishchenko Niklas Een Robert Brayton UC Berkeley Michael Case Pankaj Chauhan Nikhil Sharma Calypto Design.
On the Relation Between Simulation-based and SAT-based Diagnosis CMPE 58Q Giray Kömürcü Boğaziçi University.
Variable-Time-Frame Gate-Level Abstraction Alan Mishchenko Niklas Een Robert Brayton Alan Mishchenko Niklas Een Robert Brayton UC Berkeley UC Berkeley.
BDD-based Synthesis of Reversible Logic for Large Functions Robert Wille Rolf Drechsler DAC’09 Presenter: Meng-yen Li.
Resolution Proofs as a Data Structure for Logic Synthesis John Backes Marc Riedel Electrical.
Reducing Structural Bias in Technology Mapping
The Analysis of Cyclic Circuits with Boolean Satisfiability
Synthesis for Verification
Alan Mishchenko UC Berkeley
Enhancing PDR/IC3 with Localization Abstraction
SAT-Based Logic Optimization and Resynthesis
New Directions in the Development of ABC
Logic Synthesis CNF Satisfiability.
Simple Circuit-Based SAT Solver
Applying Logic Synthesis for Speeding Up SAT
Versatile SAT-based Remapping for Standard Cells
Integrating an AIG Package, Simulator, and SAT Solver
A Boolean Paradigm in Multi-Valued Logic Synthesis
Synthesis for Verification
SAT-Based Logic Synthesis (yes, Logic Synthesis Is Everywhere
LPSAT: A Unified Approach to RTL Satisfiability
Canonical Computation without Canonical Data Structure
SAT-Based Optimization with Don’t-Cares Revisited
Canonical Computation Without Canonical Data Structure
Robert Brayton UC Berkeley
Scalable and Scalably-Verifiable Sequential Synthesis
Automated Extraction of Inductive Invariants to Aid Model Checking
SAT-based Methods for Scalable Synthesis and Verification
Research Status of Equivalence Checking at Zhejiang University
Resolution Proofs for Combinational Equivalence
SAT-Based Logic Synthesis (yes, Logic Synthesis Is Everywhere!)
Integrating an AIG Package, Simulator, and SAT Solver
Canonical Computation without Canonical Data Structure
SAT-Based Logic Synthesis
Logic Synthesis: Past and Future
Canonical Computation without Canonical Data Structure
Alan Mishchenko University of California, Berkeley
SAT-Based Logic Synthesis (yes, Logic Synthesis Is Everywhere!)
SAT-based Methods: Logic Synthesis and Technology Mapping
Fast Min-Register Retiming Through Binary Max-Flow
SAT-Based Logic Synthesis
Alan Mishchenko Department of EECS UC Berkeley
Integrating AIG Package, Simulator, and SAT Solver
Presentation transcript:

The Synthesis of Cyclic Circuits with SAT and Interpolation By John Backes and Marc Riedel ECE University of Minnesota

Outline Motivation For Cyclic Circuits General Method Old Approach New Approach Results

Motivation Cyclic Circuit: 2 functions, 5 variables, 2 fan-in 4 gates. a b c c d e Acyclic Circuit: at least 3 fan-in 4 gates.

How can one make a cyclic circuit? Consder some acyclic circuit Pick support variablesPick target support sets in a cyclic fashion

What is wrong with the old approach? Even if a solution exists at a functional level, the gate representation may not be combinational. Old method uses BDDs. These do not scale well with the size of the circuit. Old method for functional dependencies relies on algebraic manipulation. Also not very robust and doesnt scale well.

Jiang, Mishenko, Brayton, On Breakable Cyclic Definitions, ICCAD04 Combinational on Functional Level

Jiang, Mishenko, Brayton, On Breakable Cyclic Definitions, ICCAD04

Combinational on Functional Level

a a a b b b g h f Jiang, Mishenko, Brayton, On Breakable Cyclic Definitions, ICCAD04

What is better with the new approach Uses SAT-based method for functional dependency. SAT-based cyclic analysis during synthesis. This scales better for larger benchmarks. Checks to see if functions are combinational at the functional level. If the solution is combinational at the functional level, there must exist a combinational mapping to gates.

The Notion of Dependency We say a function f is dependent on a function g (for some assignment of the variables in f s support set) if the value of g toggles the value of f. If g is a dont-care for this input assignment, then f does not depend on g.

If there exists a cycle in any induced dependency graph for a circuit, then the circuit is not combinational. If every induced dependency graph is acyclic, then the circuit is combinational. The Notion of Dependency

If there exists a cycle in any induced dependency graph for a circuit, then the circuit is not combinational. If every induced dependency graph is acyclic, then the circuit is combinational.

Checking Cyclic Dependency With SAT Consider some function f (x 0, x 1, …, x n ) and a copy of the same function with disjoint support f* (x 0 *, x 1 *, …, x n *). The satisfiability of the following clauses indicates if function f is dependent on function x i for some assignment of the support variables of f.

Functional Dependency C.-C. Lee, J.-H. R. Jiang, C.-Y. Huang, and A. Mishchenko, Scalable exploration of functional dependency by interpolation and incremental SAT solving, ICCAD 07 If SAT, the dependency function h does not exist. If UNSAT, Craig Interpolation can be used to derive an expression for h. Tells us if f 0 (x 0, x 1, …, x n ) can be expressed in terms of some function h (f 0, f 1, f 2, f 3 )

Combining Functional Dependency with Cyclic Dependencies Functional dependency tells us if a function can be represented with a specific support set. Does not tell us if functions can be represented in a cyclic fashion. We can combine the SAT instances for functional dependencies and cyclic dependencies to determine if a dependency graph is combinational. Allows us to consider a functional representation that may be more compact than an acyclic representation.

General Steps of Algorithm 1. Choose a dependency graph. 2. Locate all the cycles. 3. For each target function, create SAT instance to assert that a dependency function exists. 4. For each dependency in each cycle, create a SAT instance that asserts the dependency holds for some PI assignment. 5. Create the logical OR of the instances in steps 3 and If the instance created in step 5 is unsatisfiable, then the dependency graph is combinational.

g 1, g 2, and g 3 check for functional dependencies g 4 checks to see if there is an induced cyclic dependency

Results

Further work Develop good technology mapping strategy. Some ideas based on work in ICCAD08. Integrate into full synthesis methodology. Branch and bound. Dynamic programming. Partially completed: Biggest problem is searching for good heuristic for candidate functions.

Acknowledgements Alan Mishchenko ABC: A System for Sequential Synthesis and Verification was used to along with MiniSat to implement the SAT Based algorithm Research funding was provided by FENA