Registers of the 8086/80286 1/2002 JNM.

Slides:



Advertisements
Similar presentations
Intel 8086.
Advertisements

Block Diagram of Intel 8086 Engr.M.Zakir Shaikh
Register In computer architecture, a processor register is a small amount of storage available on the CPU whose contents can be accessed more quickly than.
MICROPROCESSORS TWO TYPES OF MODELS ARE USED :  PROGRAMMER’S MODEL :- THIS MODEL SHOWS FEATURES, SUCH AS INTERNAL REGISTERS, ADDRESS,DATA & CONTROL BUSES.
Introduction to 8086 Microprocessor
SOFTWARE ARCHITECTURE OF THE 8088 AND 8086 MICROPROCESSORS
CEN 226: Computer Organization & Assembly Language :CSC 225 (Lec#3) By Dr. Syed Noman.
Princess Sumaya Univ. Computer Engineering Dept. د. بســام كحـالــه Dr. Bassam Kahhaleh.
Azir ALIU 1 What is an assembly language?. Azir ALIU 2 Inside the CPU.
Princess Sumaya University
1 Hardware and Software Architecture Chapter 2 n The Intel Processor Architecture n History of PC Memory Usage (Real Mode)
© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e Chapter 2 The Microprocessor and its Architecture.
1 ICS 51 Introductory Computer Organization Fall 2006 updated: Oct. 2, 2006.
3-1 ECE 424 Design of Microprocessor-Based Systems Haibo Wang ECE Department Southern Illinois University Carbondale, IL Intel 8088 (8086) Microprocessor.
ICS312 Set 3 Pentium Registers. Intel 8086 Family of Microprocessors All of the Intel chips from the 8086 to the latest pentium, have similar architectures.
80x86 Processor Architecture
Gursharan Singh Tatla Block Diagram of Intel 8086 Gursharan Singh Tatla 19-Apr-17.
Unit-1 PREPARED BY: PROF. HARISH I RATHOD COMPUTER ENGINEERING DEPARTMENT GUJARAT POWER ENGINEERING & RESEARCH INSTITUTE Advance Processor.
Riyadh Philanthropic Society For Science Prince Sultan College For Woman Dept. of Computer & Information Sciences CS 251 Introduction to Computer Organization.
The 8086 Microprocessor The 8086, announced in 1978, was the first 16-bit microprocessor introduced by Intel Corporation 8086 is 16-bit MPU. Externally.
CEG 320/520: Computer Organization and Assembly Language ProgrammingIntel Assembly 1 Intel IA-32 vs Motorola
An Introduction to 8086 Microprocessor.
1 Fundamental of Computer Suthida Chaichomchuen : SCC
MOHD. YAMANI IDRIS/ NOORZAILY MOHAMED NOOR1 Addressing Mode.
Types of Registers (8086 Microprocessor Based)
Microprocessor Microprocessor (cont..) It is a 16 bit μp has a 20 bit address bus can access upto 220 memory locations ( 1 MB). It can support.
Computers organization & Assembly Language Chapter 1 THE 80x86 MICROPROCESSOR.
Block diagram of 8086.
Intel 8086 (8088) Microprocessor Structure
3.4 Addressing modes Specify the operand to be used. To generate an address, a segment register is used also. Immediate addressing: the operand is a number.
6-4 CPU-Registers, effective address General registers vs Segment registers Computer Studies (AL)
Introduction to Microprocessors Chapter 3. Programming Model (8086)  Shows the various internal registers that are accessible to the programmer.
INTRODUCTION TO INTEL X-86 FAMILY
MODULE 5 INTEL TODAY WE ARE GOING TO DISCUSS ABOUT, FEATURES OF 8086 LOGICAL PIN DIAGRAM INTERNAL ARCHITECTURE REGISTERS AND FLAGS OPERATING MODES.
Internal Programming Architecture or Model
Intel 8086 MICROPROCESSOR ARCHITECTURE
BITS Pilani Pilani Campus Pawan Sharma Lecture / ES C263 INSTR/CS/EEE F241 Microprocessor Programming and Interfacing.
Intel MP Organization. Registers - storage locations found inside the processor for temporary storage of data 1- Data Registers (16-bit) AX, BX, CX, DX.
SOFTWARE ARCHITECTURE OF THE 8088 AND 8086 MICROPROCESSORS
I NTEL 8086 M icroprocessor بسم الله الرحمن الرحيم 1.
ΜComputer Structure μProcessor Memory Bus System I/O Ports.
Chapter 12 Processor Structure and Function. Central Processing Unit CPU architecture, Register organization, Instruction formats and addressing modes(Intel.
An Introduction to 8086 Microprocessor.
UNIT Architecture M.Brindha AP/EIE
Introduction to 8086 Microprocessor
8086 Microprocessor.
Intel 8086 MICROPROCESSOR Architecture.
Basic Microprocessor Architecture
University of Gujrat Department of Computer Science
Intel 8088 (8086) Microprocessor Structure
..
Basic of Computer Organization
Microcomputer & Interfacing Lecture 1
Introduction to Assembly Language
Intel 8088 (8086) Microprocessor Structure
8086 Registers Module M14.2 Sections 9.2, 10.1.
CS-401 Computer Architecture & Assembly Language Programming
Morgan Kaufmann Publishers Computer Organization and Assembly Language
Symbolic Instruction and Addressing
CS 301 Fall 2002 Computer Organization
University of Gujrat Department of Computer Science
The Microprocessor & Its Architecture
Symbolic Instruction and Addressing
Computer Architecture CST 250
Unit-I 80386DX Architecture
Chapter 6 –Symbolic Instruction and Addressing
Intel 8086.
Chapter 8: Instruction Set 8086 CPU Architecture
8086 microprocessior PIN OUT DIAGRAM OF  Power supply and frequency signals  It uses 5V DC supply at V CC pin 40, and uses ground at V SS pin.
Part I Data Representation and 8086 Microprocessors
Presentation transcript:

Registers of the 8086/80286 1/2002 JNM

Intel 16-Bit Registers General Purpose AX AH AL 7 0 7 0 BX CX AX DX 1/2002 JNM

General Purpose Registers AX (Accumulator) – favored by CPU for arithmetic operations BX – Base – can hold the address of a procedure or variable (SI, DI, and BP can also). Can also perform arithmetic and data movement. CX – acts as a counter for repeating or looping instructions. DX – holds the high 16 bits of the product in multiply (also handles divide operations) 1/2002 JNM

Intel 16-Bit Registers Segment CS SS CS DS ES 1/2002 JNM

Segment Registers Used as base locations for program instructions, data and the stack CS – Code Segment – holds base location for all executable instructions in a program SS - Base location of the stack DS – Data Segment – default base location for variables ES – Extra Segment – additional base location for memory variables. 1/2002 JNM

Intel 16-Bit Registers Index BP SP BP SI DI 1/2002 JNM

Index Registers Contain the offset of data(variables, labels) and instructions from its base segment. BP – Base Pointer – contains an assumed offset from the SS register. Often used by a subroutine to locate variables that were passed on the stack by a calling program. SP – Stack Pointer – Contains the offset of the top of the stack. 1/2002 JNM

Index Registers Speed up processing of strings, arrays, and other data structures containing multiple elements. SI – Source Index – Used in string movement instructions. The source string is pointed to by the SI register. DI – Destination Index – acts as the destination for string movement instructions 1/2002 JNM

Intel 16-Bit Registers Status and Control IP IP Flags 1/2002 JNM

Status and Control Registers IP – Instruction Pointer – contains the offset of the next instruction to be executed. Flags Register – individual bit positions within register show status of CPU or results of arithmetic operations. Control Flags (Direction, Interrupt, Trap) Status Flags (Carry, Overflow, Sign, Zero, Auxiliary Carry, Parity) 1/2002 JNM

Flags - Status Carry (CF) – set when the result of an unsigned arithmetic operation is too large to fit into the destination. Overflow(OF) – set when the result of a signed arithmetic operation is too wide to fit into the destination. Sign(SF) – set when the result of an arithmetic or logical operation generates a negative result. Zero(ZF) – set when the result of an arithmetic or logical operation is zero. 1/2002 JNM

Flags – Status (cont) Auxiliary Carry(AF) – set when the result of an operation causes a carry from bit 3 to bit 4. Parity(PF) – reflects whether the number of 1 bits in the result of an operation is even or odd. 1 – odd, 0-even. 1/2002 JNM

Flags - Control Interrupt(IF) – dictates whether or not system interrupts can occur. 1 – enabled, 0 – disabled. Trap(TF) – determines whether or not the CPU is halted after each instruction. Allows programmers to do tracing. Direction(DF) – affects block data transfer instructions such as MOVS, CMPS. 0 – up, 1 – down. 1/2002 JNM

Instruction Execution Cycle Fetch the next operation Place it in the queue Update the program counter Decode the Instruction Perform address translation Fetch Operands from memory Execute the Instruction Perform the required calculation Store results in memory or registers Set status flags attached to the CPU 1/2002 JNM

1/2002 JNM

Absolute Address Calculation Addresses can be interpreted in 2 formats: 32-bit segment-offset address Combines a base location (segment) with an offset to represent a logical location (I.E. $08F1:0100) 20-bit absolute address (8086/88 has 20-bit address bus -> 1,048,576 different addresses) Refers to a physical address ($09010) 1/2002 JNM

Calculation of Physical Address Use segment value: $08F1 $08F1 = 0000 1000 1111 0001 Multiply by $10 $08F1 x $10 = $08F10 Add the offset value: $0100 $08F10 + $0100 = $09010 Physical Address = $ 09010 1/2002 JNM

Reversed Storage Format When storing a word value in memory, the assembler reverses the bytes. When the variable is moved to a 16-bit register, the CPU reverses the process. The value 1234h is stored as: Offset: 00 01 Value: 34 12 1/2002 JNM