1/1/ / faculty of Electrical Engineering eindhoven university of technology Processor support devices Part 3:Memory management, floating point dr.ir. A.C. Verschueren Eindhoven University of Technology Section of Digital Information Systems

1/1/ / faculty of Electrical Engineering eindhoven university of technology Separate memory management devices main memory CPU memory management Without memory management: 4 clocks With memory management: 5 clocks!

1/1/ / faculty of Electrical Engineering eindhoven university of technology Memory management timing problem Only 25% slower is not bad for a separate Memory Management Unit (MMU) ! clock data address data addressvirtualphysical controlrea d (CPU > memory management) controlrea d (memory management > memory) controlread(CPU > memory) without with

1/1/ / faculty of Electrical Engineering eindhoven university of technology Solving the timing problem (1) MMU must know virtual address before the actual memory cycle starts Use last clock cycle of memory cycle to transfer virtual address for next memory cycle –Extra hardware to keep address to memory stable –Impossible with single clock (cache) memory cycles Separate buses for virtual and physical address –Lot of pins on the memory management device !

1/1/ / faculty of Electrical Engineering eindhoven university of technology Solving the timing problem (2) The best solution is to integrate the MMU with the CPU in a single device  Only physical addresses on the external bus  Easier control of the MMU from the CPU  Memory management can be placed before on-chip caches allowing much higher system speeds!

1/1/ / faculty of Electrical Engineering eindhoven university of technology Memory management: the simple way (1) Majority of processors are 8 ‑ bit machines doesn't make sense to control a VCR with a Pentium! –The processing speed and I/O are adequate –But the memory space has become too small Marketing wants a lot of functions to be present... Consumers want an easy to use appliance... They want 'On-Screen-Display' and 'full menu control' In a lot of different languages - you simply cannot sell an English speaking TV set in Germany or France...

1/1/ / faculty of Electrical Engineering eindhoven university of technology Memory management: the simple way (2) Standard address size for 8 bit CPU’s is 16 bits –This gives bytes of memory –A moderately complex TV set control program needs on the order of 1 million bytes, mostly constant data Simple techniques can be used to achieve this –No protection is necessary (one fixed program runs) –Switching memory spaces can be software controlled –Only the Read-Only Memory needs to be this large !

1/1/ / faculty of Electrical Engineering eindhoven university of technology Windowing to extend the memory space Windowing logic can be built inside memory chips –Standard stuff for all kinds of (Flash) ROM’s –Can also save a lot of address pins! read address page register write data page register address input ROM address: Read- Only Memory 'core'

1/1/ / faculty of Electrical Engineering eindhoven university of technology 24 bits memory address ‘Memory mapper’ address extension –The 74LS610 provides 16 windows of 4096 bytes, each of these can select from 4096 of these windows in physical memory (total 16 million bytes!) CPU address 16 bits 4 bits 16 entries 12 bits

1/1/ / faculty of Electrical Engineering eindhoven university of technology Floating point hardware With minicomputers, floating point operations required a complete cabinet full of hardware Is it worth this amount of trouble? –Software implementation of the basic floating point operations takes instructions –Special instructions like 'normalise' needed for high speed Some programs have parts which execute one floating point operation every 5 to 10 instructions –’Benchmark' programs are not representative !

1/1/ / faculty of Electrical Engineering eindhoven university of technology The first single chip FP co-processors (1) Based upon a 16 bit single-chip microcomputer –AMD 9511A for the basic 32 and 64 bit operations –AMD 9512 for 32 bit basic and transcedental (sine, log) operations Attached to the main processor as I/O device –Command/status transfer by writing/reading ports –Data transfer could be done with DMA

1/1/ / faculty of Electrical Engineering eindhoven university of technology The first single chip FP co-processors (2) These devices took 1 millisecond for a 64 bits add! –The main processors at that time were 8 bits wide, these co-processors performed floating point operations times faster –Their speed is comparable to a low-end minicomputer floating point unit These devices do NOT use the IEEE standard Simply because it did not yet exist at that time

1/1/ / faculty of Electrical Engineering eindhoven university of technology The IEEE standard Intel 8087 and cousins The 8087 (at least) influenced the IEEE standard –It was an instruction set extension co-processor 20 microseconds for an 80 bits floating point add –The was much quicker (first with 32 bit bus) 'only' 2 microseconds for the same 80 bits addition The integrated FP with the main CPU With the Pentium, FP became ‘pipelined’ one FP operation per clock, at > 100 MHz !

1/1/ / faculty of Electrical Engineering eindhoven university of technology The ‘Weitek’ approach FP co- processors These use the address bus to control operations –Address 0..7:Write/read FP data registers 0..7 –Address 8..15:Add written data to FP registers 0..7 –Address :Ditto, but subtract from registers –Address :Ditto, but multiply with registers –Etcetera (just an example, of course) Speed limit: main processor read/write speed These can interface with different main processors

1/1/ / faculty of Electrical Engineering eindhoven university of technology Adhering to the IEEE standard A given set of basic FP operations must be provided –Includes division, square root and FP  Decimal The precision of operation results is precisely defined –Cutting corners to speed things up is not allowed Four different rounding modes must be provided It must be possible to calculate results with less than the maximum precision All these rules have been broken !

1/1/ / faculty of Electrical Engineering eindhoven university of technology Intel’s operating system co-processor Almost the same pins as their FP co- processor –Contains timers to generate timeouts –An interrupt controller attached to the timers and 'event' input pins –A 16 KiloByte ROM with the iRMX operating system to be run by the main processor  Fraud: not a co-processor at all!