ALICE Si-FMD 10/ Jens Jørgen Gaardhøje, NBI, Forward Multiplicity Detector (status and progress) Si-FMD (Forward Multiplicity Detector) oSi-strip Ring counters (5) with channels o-5.1<  < -1.7; 1.7<  < 3.4 oOff-line charged particle multiplicity for A+A, p+p oFluctuations event-by-event, flow analysis oGeometry and integration defined.Prototyping of mech. Supports. oFinal Si-sensor design ongoing. oRead out chain (FEE-BEE-DAQ) defined.Prototyping ongoing. oPerformance/simulations oTDR in preparation. oConcerns: ’ambient’ temperature, material

ALICE Si-FMD 10/ Jens Jørgen Gaardhøje, NBI, Si-FMD  5 Si-strip rings segmented into channels  Rapidity coverage from ITS (1.7) to 5.1.  Segmentation sufficient for ‘Poisson’ analysis Main Off-line charged particle multiplicity studies Average multiplicity (entropy, stopping) Fluctuations (phase transitions) Flow (thermalisation, hydrodynamics) Si3 Si2 Si1

ALICE Si-FMD 10/ Jens Jørgen Gaardhøje, NBI, Forward rapidity physics at LHC pppp RHIC  s nn = 200AGeV Plateau at LHC –6<  <+6 ?

ALICE Si-FMD 10/ Jens Jørgen Gaardhøje, NBI, CERN Maquette 1:1 Si1 (inner)Si1(outer) V0-R T0-R Absorber ITS-pixels

ALICE Si-FMD 10/ Jens Jørgen Gaardhøje, NBI, Mechanical Installation

ALICE Si-FMD 10/ Jens Jørgen Gaardhøje, NBI, FMD Cabling on muon side Digitized signals, HV and control

ALICE Si-FMD 10/ Jens Jørgen Gaardhøje, NBI, Si1 mechanics model 1:1 Si detectors Support plate Digitizer card Beam pipe support ring Outer ring not shown Engineering study in progress to minimize material, maximize rigidity

ALICE Si-FMD 10/ Jens Jørgen Gaardhøje, NBI, Heat dissipation oHeat dissipated by FE electronics of one Si detector ring: VA1’’ preamp chip (128 channels): 235 mW  80 chips = 19 W / ring Read-out electronics and power distribution:  5 W/ring Cooling: air flow between Si detector and support plate radiation from VA chips to support. active (water) cooling of support plate is considered Detailed cooling studies (simulations of heat profile) need to be done. Presently, the temperature at the FMD, T0, V0 location is >70 deg. due to ITS heat dissipation. Effective general cooling of this region required !

ALICE Si-FMD 10/ Jens Jørgen Gaardhøje, NBI, Left Side: Si2 & Si3 Details of mounting to be finalized

ALICE Si-FMD 10/ Jens Jørgen Gaardhøje, NBI, Si rings manufactured of 6” wafers 512 Inner: Rin=4.2 cm Rout=17.2 cm Outer: Rin=15.4 cm Rout=28.4 cm 10x2x512= x2x256= Possible suppliers: Micron, UK Hamamatsu, JP

ALICE Si-FMD 10/ Jens Jørgen Gaardhøje, NBI, Coverage in pseudorapidity Constraints: Vacuum tube outer envelope: 42 mm, Outer radius, ITS, Absorber, cables Background from secondaries(small angles) Design criteria: Largest possible  coverage Largest symmetry left and right Overlap between systems Si1: Out: 1.70<  <2.29 In: 2.01<  <3.40 Si2: Out: -2.29<  <-1.7 In: -3.68<  <-2.28 Si3: In: -5.09<  <-3.68 Vertex shift (10cm): |d  |  0.1 

ALICE Si-FMD 10/ Jens Jørgen Gaardhøje, NBI, Details of Si sensors Hamamatsu, Micron

ALICE Si-FMD 10/ Jens Jørgen Gaardhøje, NBI, Adjusted acceptance

ALICE Si-FMD 10/ Jens Jørgen Gaardhøje, NBI, Hybrid with Viking PA chips VA preamp+shaper: 128 ch Connector(s) for power, control, read-out Other components Hybrid cards contain:  FE–Preampl. chips  Bias voltages distribution  Gate/strobe distribution  Read-out clock distribution  Detector bias connection Si detector

ALICE Si-FMD 10/ Jens Jørgen Gaardhøje, NBI, FMD RO strategy FMD Segment ON DETECTOR Digital serial links (15-20 m) Digital serial links (15-20 m) Trigger & Slow Ctrl IN CAVERN IN COUNTING ROOM Slow control & Trigger Slow control & Trigger Detector Data Link (50-60 m) Detector Data Link (50-60 m) FMD RCU VA 1 ring: 10/20 segments 2 Digitizers 1 RCU per side 1 DDL per side Full FMD: 70 segments 10 Digitizers 2 RCU’s 2 DDL’s FMD Read-Out and Control Electronics Analog serial link (10 MHz)  0.5 m Analog serial link (10 MHz)  0.5 m VA read-out control VA read-out control Local Controller DDL - INT Slow-Control Interface TTC-RX BOARD CTRL Data receiver FMD Digitizer ALTRO CTRL Read-out CTRL CTRL BSN, 21 Nov 2002

ALICE Si-FMD 10/ Jens Jørgen Gaardhøje, NBI, Si-FMD electronics overview SI-FMD channel count Note: We have increased the number of strips, but use more integrated FE chips – red values are changed. Segments (wafers) Phi sectors Radial strips FE channels VA chips (128 ch/chip) ALTRO chips FMD Digitizers FMD RCU Si1 inner , Si1 outer , Si2 inner , Si2 outer , Si , Total system ,

ALICE Si-FMD 10/ Jens Jørgen Gaardhøje, NBI, FMD FEE test setup BSN, 21 Nov 2002 FMD FEE test CTRL Power Biases Power Biases Clock 10 MHz Clock 10 MHz Trig in ALTRO tester ALTRO CTRL Ext clock Ext trigger Si detector VA Labview DAQ NBI test board: - generates trigger + pulse on Si det - level adaption of VA-to-ALTRO - VA read-out clock + controls - ALTRO digitization clock (sync.)

ALICE Si-FMD 10/ Jens Jørgen Gaardhøje, NBI, Si-FEE-Digitizer prototyping at NBI ALTRO tester Si-strip detector + VA’’ preamp VA’’ read-out controller DAQ/ Labview

ALICE Si-FMD 10/ Jens Jørgen Gaardhøje, NBI, First prototype test results Trigger Si+ Preamp Out Altro Out Output from VA chip: (128 channels multiplexed into serial read-out) Note: 3 bad Si/VA channels Output from ALTRO: (128 time bins are digitized) Note: general shape + 3 bad channels repeated Noise still too high Timing still not stable

ALICE Si-FMD 10/ Jens Jørgen Gaardhøje, NBI, Slow Controls Follow main strategy DCS Detector CAEN ? PVSS II Preamps CAEN ? Ethernet Database(s) OPC client DIM client High Voltage Preamps User interface PVSS II HVLV FMD Control room (ACR) [FSM?] Crate Control PCI-CAN? CAEN OPCserver PVSS II OPS client PCI-CAN? CAEN OPCserver PVSS II OPC client DIMserver Digitizers FMD Digitizers PCI-CAN? ? PVSS II OPC client C 2 28/02/03 EE FMD-RCU (PCI? VME?) 20 LV P 2 DDL PCI-Profibus Ethernet is considered as alternative P? ? 10 LVL 0 trig TTC Counting room Cavern In magnet

ALICE Si-FMD 10/ Jens Jørgen Gaardhøje, NBI, Charged particle occupancy including secondaries 20  sectors 512 strips each channels 20  sectors 512 strips each channels 40  sectors 256 strips each channels Have increased number of strips by factor of 2 using ’128 ch VA-prime’ PA chip at practically same cost => average occupancy <1 for most strips! x Si-1 inner Si-3Si-1 outer

ALICE Si-FMD 10/ Jens Jørgen Gaardhøje, NBI, Background from Secondaries Si1 outer Si1 inner Si2 inner Si3 Primaries Beam pipe ITS T0,V0,Abs, frames

ALICE Si-FMD 10/ Jens Jørgen Gaardhøje, NBI, Reconstruction of ’true’ multiplicity 10 HIJING events 1 HIJING event Primaries+secondaries Primaries Input dist and reconstructed HijingGeant= R * Hijing R = R(  ) response matrix

ALICE Si-FMD 10/ Jens Jørgen Gaardhøje, NBI, Iterative convolution of trial spectrum O = R * TrueSpec O(0)= R(0)* H TrueSpec(1)=O/O(1)*H O(1)= R(1)* TrueSpec(1) …Continue until O(n)  O Test of flat input distribution

ALICE Si-FMD 10/ Jens Jørgen Gaardhøje, NBI, Si-FMD timetable (1) AFRONT END (FE) READ OUT ELECTRONICSCompleted 1Demonstrate functionality of conceptual layout of FEE (Viking PA chip, control system, interface to ALTRO test board) August Final choice of VA pre-ampl. chip. RO test 3Test FEE system coupled to sample Si detector. Source and electron beam tests. 4Design, construction and test of prototype FMD digitizer card (FMDD), RO test with ’mini’ FMD-RCU 5Full Si detector element + electronics chain RO with realistic RCU and DDL link to DAQ. June 1, 2004 BMECHANICS AND INTEGRATIONCompleted 1Full scale model manufactured (Si1)February 1, Cabling and Cooling issues resolvedJune 1, Full integration sequence decidedJune 1, 2003

ALICE Si-FMD 10/ Jens Jørgen Gaardhøje, NBI, Si-FMD timetable (2) C.SILICON DETECTORCompleted by 1Complete market surveyMay, Define final specsOctober Place order for prototype with industryNovember Delivery Si-wafer prototypeFebruary Start production of Si-hybrid FEE cardDecember Delivery prototype hybridMarch Si prototype test with FEE and BEE test RO setupApril Place final order for Si with industryOctober 2004 Pre-assembly test July-Nov 2004 Construction, assembly, test at RHIC 2005 Installation June-Sept 2006

ALICE Si-FMD 10/ Jens Jørgen Gaardhøje, NBI, Si-FMD, TO,VO TDR time table. oFair amount of written material exists already (T0 100 pgs, Si-FMD 50 pgs, V0 20 pgs) oApril 15. Collect first detector chapters. oJune ’03. Editorial meeting. 1rst draft. oSummer ’03 Si-FMD electronics chain test. oJune ’03 T0 test beam oAugust ’03 V0 test beam oTDR writing: fall 2003

ALICE Si-FMD 10/ Jens Jørgen Gaardhøje, NBI, Techical Design Report Alice collab list. (5pgs) Summary of contents (2pgs) Table of contents. List of tables and figs.(4pgs) Color pictures of selected det. elements etc. (6pgs) 1. Physics objectives and design considerations T0, V0, Si-FMD trigger, timing, on-line mult, off-line mult, fluct, bgd rejection, overall performance, coverage etc...(10 pgs) 2. Design objectives, mechanical structure, Integration T0, V0, Si-FMD mounting, tolerances, clearances, inst. seq., cooling, cabling... (10pgs) 3. T0 (40 pgs) 4. V0 (40 pgs) 5. Si-FMD (40 pgs) 6. Installation, slow control, DAQ, safety. (10 pgs) 7. Organization(5 pgs) Group org., construction, installation, cost 8. References. (4pgs) 9. Index(2 pgs) (approx. 180 pgs)

ALICE Si-FMD 10/ Jens Jørgen Gaardhøje, NBI, Tasks and decisions for Weekly meetings (1) 1) Si sensors: - define final specs of sensor properties - negotiate price again with Hamamatsu and Micron - choose company - order prototype 2) Voltage supplies - define Voltage requirements (Volt, current, remote control and DCS) - investigate market (check out ITS or other Si systems in ALICE) 3) Bonding - decide on bonding strategy (CERN or other) - make arrangement with bonder 4) FEE-preamplifier card. - define final specs of FEE hybrid card - define interface to ALTRO -digitizer card and other slow controls. - define strategy: home built hybrid card with VA-prime from IDEAS or design and production by IDEAS and production for card? -updated cost estimate for industrial design and production (IDEAS)

ALICE Si-FMD 10/ Jens Jørgen Gaardhøje, NBI, Tasks and decisions for Weekly meetings(2) 5) Digitizer card (ALTRO board) -define interface to FEE and RCU - define necessary modifications to standard ALTRO boards 6) RCU card. - define interface to digitizer card (ALTRO board) - define necesary modifications to RCU 7) DDL and connection to DAQ -define modifications needed, if any 8) cabling and services, cooling - define cable types and length. - define connectors - define own cooling needs - define placement of cards/DDL etc in ALICE 9) Mechanical - define mechanical mounts for Si1, Si2, Si3. 10) Slow Control and DAQ communication - define tasks to be done -collect information and establish contact with DCS and DAQ groups.

ALICE Si-FMD 10/ Jens Jørgen Gaardhøje, NBI, Extra’s

ALICE Si-FMD 10/ Jens Jørgen Gaardhøje, NBI, Front end electronics REQUIREMENTS: Adapted for 5-25pF capacitance (300  m Si, 0.5 cm2: 25pF, 1MIP: e-) Dynamic range: 0-20 MIPS Radiation hardness: >200kRad Peaking time: 1-2  s Low noise (good S/N) High integration Sample/hold and serial read- out, 10 MHz clock Moderate power consumption Simple slow controls and power reg. Affordable cost VA1 prime 2 (Viking-IDEAS): Input capacitance: < 30 pF 0-20 MIPs >1MRad (0.35  m tech.) 1-3  s 475 e- at 25 pF => S/N 20: Mhz clock 1.3 mW/ch Test system available OK

ALICE Si-FMD 10/ Jens Jørgen Gaardhøje, NBI, Multiplicity resolution

ALICE Si-FMD 10/ Jens Jørgen Gaardhøje, NBI, Reconstructed multiplicity. Average and width Background Subtracted All hits reconstructed  1.7  3.4

ALICE Si-FMD 10/ Jens Jørgen Gaardhøje, NBI, Background  =2.4  =1.31  =1.73 Si3 Si2outer Si2inner Si1outer Si1inner Alla Maevskaia ALICE Week 9 September 2003