Progress with the 3T Demonstrator Proposal A.Marchioro CERN April 2010

Module overview A.Marchioro / April 20102

Status of Verilog Model (work of D. Felici, Master Student from U. of Roma) Completed first architecture including – Cluster reject – Top-to-bottom “hit image” transmission – Z-alignment – 3x3 and 3x5 mask search Capable of handling MC physics events and matching with off-line filter A.Marchioro / April 20103

250um 150 um 100 um 2* um 100um 150 um 250 um TFEA AUX 16 mm 6 x ( ) mm DC-DC Module size = [6 * 8] x [3 * ] mm … TFEA Option 1: WB & BB A.Marchioro / April Cooling

Sensor 250um C4 100 um ASIC 100 um C4 100 um Substrate 700 um C4 100 um ASIC 100um C4 100 um Sensor 250 um ROA 16 mm 6 x (8.0) mm AUX Module size = [6 * 8] x [3 * ] mm … Option 2: TSV & BB A.Marchioro / April … TSV Z r  r

3T FE+Sensor “Emulator” floorplan A.Marchioro / April Upper layer chip Lower layer chip C4 bump Mode=UPPER Emulating Sensor Mode=UPPER Emulating Sensor Mode=LOWER Emulating RO chip Mode=LOWER Emulating RO chip

3T chip Top Level Schematic A.Marchioro / April 20107

3T chip layout in 0.25um A.Marchioro / April 20108

Status of 3T chip design Logic, interconnectivity and layout done 100% IO pads being modified to allow back-side coarse density TSV interconnect Still refining final design guidelines for bump- bonding (compatibility of BB and WB on same layer): – IBM (C4) – ASE modified (smaller pitch, 100 um possible) ASE – ex-NXP (special in house process) A.Marchioro / April 20109

Chips on Wafer 10 Reticle

250um 150 um 250 um 2* um 250 um 150 um 250 um 3T AUX Substrate 16 mm 1 x ( ) mm DC-DC 3T Proto Simple Module A.Marchioro / April Cooling

3T single chip Substrate … 3T Pseudo-Sensor 3T Proto module A.Marchioro / April Substrate Cooling

Proposal to (at least) 2 companies Phase 1: – Single 2x3T chip on a substrate Phase 2: – Single face module with 18x3T+pseudo-sensor Phase 3: – Double face module with emulator chips Phase 4: – Full module with real read-out chips A.Marchioro / April

Selection of manufacturers Full and very detailed proposal from Endicott Interconnect in hands 2 nd proposal from ex NXP expected for this week Third (Far-East) option? A.Marchioro / April

Benefit of exercise From an electronics point-of-view the difficulty of (any) triggering module is primarily in the interconnect, not in FE or logic design The second most difficult problem is to realize all functionality within available power budget (<100 uW/pixel) Exercise extremely useful to study: – Low-mass high-density interconnect technologies TSV and Mixed WB and BB techniques – Low power design – Integration tests: Opto components Power converters Cooling – Overall tracker geometry – Identify good partner for subcontracting (modest-scientific-value) assembly activities A.Marchioro / April

Spare slides A.Marchioro / April

Functional block diagram A.Marchioro / April FE Ev Store Data Link Trigger Link Trigger Logic Pixel Block Upper Layer Lower Layer Local Trigger Link FE Ev Store Data Link Trigger Link Trigger Logic Local Trigger Link CLK & Cntrl Active Inactive

Single Channel size: 100 x 1750 um Analog circuit: 100 x 750 um2 Bias, Dacs etc: 100 x 200 um2 Bump-bond pad: 90 x 90 um2 Event Memory depth: 6 usec -> memory length: 40 x 6 ~ 256 bits -> cell size: 2.1 um2 -> block size: 750 um2 ~ 28x28 um2 (rounded to 100x100 um2) Coincidence logic: Lookup SRAM -> 100x100 um2 Read-Out Logic: 80 x 80 um2 Channel Configuration regs: 100 x 100 um2 DACs Analog FE Coincidence SRAM Pixel block Floorplan DACs Analog FE Coincidence SRAM R-O 18A.Marchioro / April 2010 DACs Analog FE Coincidence SRAM DACs Analog FE Coincidence SRAM R-O DACs Analog FE Coincidence SRAM DACs Analog FE Coincidence SRAM R-O DACs Analog FE Coincidence SRAM DACs Analog FE Coincidence SRAM R-O Configuration Shared Routing and Logic Shared Logic and Routing