CBP 2002Repository1 Overview PC Structure 1

CBP 2002Repository2

CBP 2002Repository3 CPU Caches System Bus Memory I/O controllers bridges Disk, Mouse Displays Keyboards Ethernet I/O Buses

CBP 2002Repository4 caclulator

CBP 2002Repository5 Stonehenge

CBP 2002Repository6

CBP 2002Repository7 Sam 4 Series Master Data Memory Code Memory ALU r1 r2 r0 X Y W XY W mar mdr

CBP 2002Repository8 Sam 4 Series Master Data Memory Code Memory ALU r1 r2 r0 X Y W XY W mar mdr

CBP 2002Repository9 Sam 4 Bits Data Memory Code Memory ALU r1 r2 r0 X Y W XY W mar mdr

CBP 2002Repository10 Computer Clipart

CBP 2002Repository11 Sam 4 outline

CBP 2002Repository12 Memory CPU Arithmetic Logic Unit (ALU) CPU Control Unit Input Output

CBP 2002Repository13 Data Memory mar mdr X Y W Y W r1 r2 r0 X PC Code Memory Sam4 Bits X Y W Y W r1 r2 r0 X mar mdr

CBP 2002Repository14 Data Memory mar mdr X Y W Y W r1 r2 r0 X PC Code Memory Sam4 Bits X Y W Y W r1 r2 r0 X mar mdr

CBP 2002Repository15 Memory Cells

CBP 2002Repository16 Mem reg and inst for Sam r3 unusedrtrsrdldr opcode destination Source regs

CBP 2002Repository17 Spreadsheet Bits

CBP 2002Repository18 Timing diag bits 1 T1T2T3T4T5 FetchDecode, Reg Op ALU OpMem Access Reg Write

CBP 2002Repository19 Timing Diag Worksheet T1T2T3T4T5 FetchDecode, Reg Op ALU OpMem Access Reg Write

CBP 2002Repository20 Timing diag bits 1 T1T2T3T4T5 Fetch Decode, Reg Op ALU Op Mem Access Reg Write T1T2T3T4T5 Fetch Decode, Reg Op ALU Op Mem Access Reg Write T1T2T3T4T5 Fetch Decode, Reg Op ALU Op Mem Access Reg Write T1T2T3T4T5 Fetch Decode, Reg Op ALU Op Mem Access Reg Write

CBP 2002Repository21 Reg and ALU Bits (nonsam) Memory Register ALU r0 r1 r2 r3 r11 r0 ALU

CBP 2002Repository22 More Reg ALU Bits (nonsam)

CBP 2002Repository23 MEM CPU DISK IO MEM CPU DISK IO

CBP 2002Repository24 Turing Machine Bits S0 R ……

CBP 2002Repository25 Logic gates

CBP 2002Repository26 Buses Correctly Sized Components !

CBP 2002Repository27 Buses Correctly Sized Components !

CBP 2002Repository28 This Time ALU Mem Reg MemReg ALU Mem Reg MemReg

CBP 2002Repository29 This Time ALU Mem Reg MemReg

CBP 2002Repository30 coffee

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CBP 2002Repository32 Pipeline template

CBP 2002Repository33 Pipeline template

CBP 2002Repository34 Pipeline template

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CBP 2002Repository36

CBP 2002Repository37 Pipeline template

CBP 2002Repository38 Performance incl. Stalls 5 cycles gives 5 loads so we have 1 cycle per load (CPL = 1) Speedup = 5. This is of course just the pipeline depth. (Assuming there are no stalls).

CBP 2002Repository39 Increasing Shirt Throughput idle running idle running A. Wash then Dry B. Wash then Dry and Reload Wash time

CBP 2002Repository40 blank

CBP 2002Repository41 T1T2T3T4T5 FetchDecode, Reg Op ALU OpMem Access Reg Write

CBP 2002Repository42 T1T2T3T4T5 Fetch Decode, Reg Op ALU Op Mem Access Reg Write

CBP 2002Repository43 T1T2T3T4T5 Fetch Decode, Reg Op ALU Op Mem Access Reg Write