Cache Memory Exercises. Questions I Given: –memory is little-endian and byte addressable; memory size; –number of cache blocks, size of cache block –An.

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Presentation transcript:

Cache Memory Exercises

Questions I Given: –memory is little-endian and byte addressable; memory size; –number of cache blocks, size of cache block –An instruction lw $t0, x or lbu $t0, x; Determine –HIT or MISS? –What value is in $t0?; and –Show the cache after word is brought in if needed

Address (binary) Contents (Hex) aa bb cc dd ff ee a bc de f0 1a a 3a 4a 5a a 7a 8a 9a b 2b 3b 4b b2 b3 b4 b c1 c2 c3 c d1 d2 d3 d e1 e2 e3 e f1 f2 f3 f a1 a2 a3 a c 3c 4c 5c d 3d 4d 5d VTagdata(hex) a lbu $t0, x # x = Question 1: cache HIT or MISS? What is in $t0? Draw the cache after data is brought in Assume memory is little-endian and byte addressable; cache block = 1 word; Cache holds 4 blocks of data ( 4 words)

Address (binary ) Contents (Hex) aa bb cc dd ff ee a bc de f0 1a a 3a 4a 5a a 7a 8a 9a b 2b 3b 4b b2 b3 b4 b c1 c2 c3 c d1 d2 d3 d e1 e2 e3 e f1 f2 f3 f a1 a2 a3 a c 3c 4c 5c d 3d 4d 5d VTagdata(hex) Ffee lbu $t0, x # x = Question 2: cache HIT or MISS? What is in $t0? Draw the cache after data is brought in Assume memory is little-endian and byte addressable; cache block = 1 word; Cache holds 4 blocks of data ( 4 words)

Address (binary) Contents (Hex) aa bb cc dd ff ee a bc de f0 1a a 3a 4a 5a a 7a 8a 9a b 2b 3b 4b b2 b3 b4 b c1 c2 c3 c d1 d2 d3 d e1 e2 e3 e f1 f2 f3 f a1 a2 a3 a c 3c 4c 5c d 3d 4d 5d VTagdata(hex) lbu $t0, x # x = Question 3: cache HIT or MISS? What is in $t0? Draw the cache after data is brought in Assume memory is little-endian and byte addressable; cache block = 1 word; Cache holds 4 blocks of data ( 4 words)

Address (binary) Contents (Hex) ff ee a bc de f0 1a a 3a 4a 5a a 7a 8a 9a b 2b 3b 4b b2 b3 b4 b c1 c2 c3 c d1 d2 d3 d e1 e2 e3 e f1 f2 f3 f a1 a2 a3 a c 3c 4c 5c d 3d 4d 5d VTagdata(hex) lbu $t0, x # x = Question 4: cache HIT or MISS? What is in $t0? Draw the cache after data is brought in Assume memory is little-endian and byte addressable; cache block = 1 word; Cache holds 4 blocks of data ( 4 words)

Address (binary) Contents (Hex) aa bb cc dd ff ee a bc de f0 1a a 3a 4a 5a a 7a 8a 9a b 2b 3b 4b b2 b3 b4 b c1 c2 c3 c d1 d2 d3 d e1 e2 e3 e f1 f2 f3 f a1 a2 a3 a c 3c 4c 5c d 3d 4d 5d VTagdata(hex) lbu $t0, x # x = Question 5: cache HIT or MISS? What is in $t0? Draw the cache after data is brought in Assume memory is little-endian and byte addressable; cache block = 1 word; Cache holds 4 blocks of data ( 4 words)

Cache Question II-1 Suppose: 256 bytes of memory, cache holds 4 blocks, each block is 1 word. What is the cache size? Answer: aaaaaaaa  t t t t i i o o cache: valid tag data Cache size: (4+1+32)*4 bits

Cache Question II-2 Suppose: 256 bytes of memory, cache holds 8 blocks, each block is 1 word. What is the cache size? Answer: aaaaaaaa  t t t i i i o o cache: valid tag data Cache size: (3+1+32)*8 bits

Question II-3 What is the cache size (total number of bits) for a cache that holds 64KB of data (block == 1 word; 2**32 bytes of memory) Answer: 64KB == 16K words; –16K = (2**4) *(2**10) = 2**14 –So 14 bits are needed for the cache index Tag size = 32 – = 16 bits Cache size = (1 + ( ) + 32) * (2**14) = 784 K bits = 98 KB