Caleb Serafy and Ankur Srivastava Dept. ECE, University of Maryland

Slides:



Advertisements
Similar presentations
THERMAL-AWARE BUS-DRIVEN FLOORPLANNING PO-HSUN WU & TSUNG-YI HO Department of Computer Science and Information Engineering, National Cheng Kung University.
Advertisements

A Graph-Partitioning-Based Approach for Multi-Layer Constrained Via Minimization Yih-Chih Chou and Youn-Long Lin Department of Computer Science, Tsing.
Cadence Design Systems, Inc. Why Interconnect Prediction Doesn’t Work.
UCLA Modeling and Optimization for VLSI Layout Professor Lei He
Reap What You Sow: Spare Cells for Post-Silicon Metal Fix Kai-hui Chang, Igor L. Markov and Valeria Bertacco ISPD’08, Pages
3D-STAF: Scalable Temperature and Leakage Aware Floorplanning for Three-Dimensional Integrated Circuits Pingqiang Zhou, Yuchun Ma, Zhouyuan Li, Robert.
National Tsing Hua University Po-Yang Hsu,Hsien-Te Chen,
Paul Falkenstern and Yuan Xie Yao-Wen Chang Yu Wang Three-Dimensional Integrated Circuits (3D IC) Floorplan and Power/Ground Network Co-synthesis ASPDAC’10.
Coupling-Aware Length-Ratio- Matching Routing for Capacitor Arrays in Analog Integrated Circuits Kuan-Hsien Ho, Hung-Chih Ou, Yao-Wen Chang and Hui-Fang.
FastPlace: Efficient Analytical Placement using Cell Shifting, Iterative Local Refinement and a Hybrid Net Model FastPlace: Efficient Analytical Placement.
Krit Athikulwongse, Dae Hyun Kim, Moongon Jung, and Sung Kyu Lim
Noise Model for Multiple Segmented Coupled RC Interconnects Andrew B. Kahng, Sudhakar Muddu †, Niranjan A. Pol ‡ and Devendra Vidhani* UCSD CSE and ECE.
1 Thermal Via Placement in 3D ICs Brent Goplen, Sachin Sapatnekar Department of Electrical and Computer Engineering University of Minnesota.
The loss function, the normal equation,
Distributed Algorithms for Secure Multipath Routing
Multiobjective VLSI Cell Placement Using Distributed Simulated Evolution Algorithm Sadiq M. Sait, Mustafa I. Ali, Ali Zaidi.
Last Time Pinhole camera model, projection
Chapter 5 Interconnect RLC Model n Efficient capacitance model Efficient inductance model Efficient inductance model RC and RLC circuit model generation.
Layer Assignment Algorithm for RLC Crosstalk Minimization Bin Liu, Yici Cai, Qiang Zhou, Xianlong Hong Tsinghua University.
Localized Techniques for Power Minimization and Information Gathering in Sensor Networks EE249 Final Presentation David Tong Nguyen Abhijit Davare Mentor:
EE4271 VLSI Design Interconnect Optimizations Buffer Insertion.
Supply Voltage Degradation Aware Analytical Placement Andrew B. Kahng, Bao Liu and Qinke Wang UCSD CSE Department {abk, bliu,
Interconnect Network Modeling Motivation: Investigate the response of a complex interconnect network to external RF interference or internal coupling between.
An Impulse-Response Based Methodology for Modeling Complex Interconnect Networks Zeynep Dilli, Neil Goldsman, Akın Aktürk Dept. of Electrical and Computer.
Lecture #25a OUTLINE Interconnect modeling
Accurate Pseudo-Constructive Wirelength and Congestion Estimation Andrew B. Kahng, UCSD CSE and ECE Depts., La Jolla Xu Xu, UCSD CSE Dept., La Jolla Supported.
Delay and Power Optimization with TSV-aware 3D Floorplanning M. A. Ahmed and M. Chrzanowska-Jeske Portland State University, Oregon, USA ISQED 2014.
Floorplanning and Signal Assignment for Silicon Interposer-based 3D ICs W. H. Liu, M. S. Chang and T. C. Wang Department of Computer Science, NTHU, Taiwan.
Neural Networks Lecture 17: Self-Organizing Maps
CDCTree: Novel Obstacle-Avoiding Routing Tree Construction based on Current Driven Circuit Model Speaker: Lei He.
1 A Novel Metric for Interconnect Architecture Performance Parthasarathi Dasgupta, Andrew B. Kahng, Swamy V. Muddu Dept. of CSE and ECE University of California,
An Impulse-Response Based Methodology for Modeling Complex Interconnect Networks Zeynep Dilli, Neil Goldsman, Akın Aktürk Dept. of Electrical and Computer.
Noise and Delay Uncertainty Studies for Coupled RC Interconnects Andrew B. Kahng, Sudhakar Muddu † and Devendra Vidhani ‡ UCLA Computer Science Department,
Dan Simon Cleveland State University
Through Silicon Vias EECS713 Daniel Herr.
A Methodology for Interconnect Dimension Determination By: Jeff Cobb Rajesh Garg Sunil P Khatri Department of Electrical and Computer Engineering, Texas.
Introduction to Routing. The Routing Problem Apply after placement Input: –Netlist –Timing budget for, typically, critical nets –Locations of blocks and.
MGR: Multi-Level Global Router Yue Xu and Chris Chu Department of Electrical and Computer Engineering Iowa State University ICCAD
Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Topics n Interconnect design. n Crosstalk. n Power optimization.
1 Coupling Aware Timing Optimization and Antenna Avoidance in Layer Assignment Di Wu, Jiang Hu and Rabi Mahapatra Texas A&M University.
Seongbo Shim, Yoojong Lee, and Youngsoo Shin Lithographic Defect Aware Placement Using Compact Standard Cells Without Inter-Cell Margin.
TSV-Aware Analytical Placement for 3D IC Designs Meng-Kai Hsu, Yao-Wen Chang, and Valerity Balabanov GIEE and EE department of NTU DAC 2011.
Johann Knechtel, Igor L. Markov and Jens Lienig University of Michigan, EECS Department, Ann Arbor USA Dresden University of Technology, EE Department,
Analytic Placement. Layout Project:  Sending the RTL file: −Thursday, 27 Farvardin  Final deadline: −Tuesday, 22 Ordibehesht  New Project: −Soon 2.
Massachusetts Institute of Technology 1 L14 – Physical Design Spring 2007 Ajay Joshi.
Closing the Smoothness and Uniformity Gap in Area Fill Synthesis Supported by Cadence Design Systems, Inc., NSF, the Packard Foundation, and State of Georgia’s.
Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Topics n Interconnect design. n Crosstalk. n Power optimization.
A Faster Approximation Scheme for Timing Driven Minimum Cost Layer Assignment Shiyan Hu*, Zhuo Li**, and Charles J. Alpert** *Dept of ECE, Michigan Technological.
Optimal Placement of Femto Base Stations in Enterprise Femtocell Networks Adviser: Frank, Yeong - Sung Lin Present by Li Wen Fang.
Test Architecture Design and Optimization for Three- Dimensional SoCs Li Jiang, Lin Huang and Qiang Xu CUhk Reliable Computing Laboratry Department of.
Clock-Tree Aware Placement Based on Dynamic Clock-Tree Building Yanfeng Wang, Qiang Zhou, Xianlong Hong, and Yici Cai Department of Computer Science and.
TSV-Constrained Micro- Channel Infrastructure Design for Cooling Stacked 3D-ICs Bing Shi and Ankur Srivastava, University of Maryland, College Park, MD,
Prof. D. Wilton ECE Dept. Notes 24 ECE 2317 Applied Electricity and Magnetism Notes prepared by the EM group, University of Houston.
HEAT TRANSFER FINITE ELEMENT FORMULATION
CS270 Project Overview Maximum Planar Subgraph Danyel Fisher Jason Hong Greg Lawrence Jimmy Lin.
Introduction to Clock Tree Synthesis
Chapter 4: Secs ; Chapter 5: pp
A Novel Timing-Driven Global Routing Algorithm Considering Coupling Effects for High Performance Circuit Design Jingyu Xu, Xianlong Hong, Tong Jing, Yici.
1 Double-Patterning Aware DSA Template Guided Cut Redistribution for Advanced 1-D Gridded Designs Zhi-Wen Lin and Yao-Wen Chang National Taiwan University.
RTL Design Flow RTL Synthesis HDL netlist logic optimization netlist Library/ module generators physical design layout manual design a b s q 0 1 d clk.
Algorithms and Networks
VLSI Physical Design Automation
Partial Reconfigurable Designs
Graphcut Textures:Image and Video Synthesis Using Graph Cuts
The Interconnect Delay Bottleneck.
Microwave Passives Anurag Nigam.
Multi-modality image registration using mutual information based on gradient vector flow Yujun Guo May 1,2006.
Errors due to process variations
The loss function, the normal equation,
Mathematical Foundations of BME Reza Shadmehr
Presentation transcript:

Caleb Serafy and Ankur Srivastava Dept. ECE, University of Maryland Coupling-Aware Force Driven Placement of TSVs and Shields in 3D-IC Layouts Caleb Serafy and Ankur Srivastava Dept. ECE, University of Maryland 3/31/2014

3D Integration Vertically stack chips and integrate layers with vertical interconnects Through Silicon Vias (TSVs) Advantages: Smaller footprint area Shorter global wirelengths Heterogeneous Integration Disadvantages: TSV-TSV coupling TSV reliability Increased power density Trapped heat effect 3/31/2014

TSV-TSV Coupling SOLUTIONS: TSV spacing and TSV shielding TSVs have large capacitance to substrate Substrate is conductive: low noise attenuation Coupling between TSVs must be minimized in order to maximize switching speed SOLUTIONS: TSV spacing and TSV shielding 3/31/2014

TSV spacing Spacing between TSVs can reduce coupling But requires large distance Shield insertion can reduce coupling when spacing is small 3/31/2014

TSV spacing Spacing between TSVs can reduce coupling But requires large distance Shield insertion can reduce coupling when spacing is small d=12 3/31/2014

TSV Shielding Shielding: place a grounded conductor between two wires EM waves cannot pass through shield, reducing coupling between wires Guard ring is less effective with TSVs TSVs require shielding throughout the thickness of the silicon substrate use GND TSV as shield Optimal shield placement requires chip-scale coupling models Analog Transistor 3/31/2014

Previous Work Geometric model of coupling Shield insertion algorithm [Serafy et. al GLSVLSI’13] Geometric model of coupling Circuit model of coupling too complex for chip-scale optimization Developed model of S-parameter based on relative TSV positions Used curve fitting on HFSS simulation data Shield insertion algorithm Based on fixed signal TSV locations, place shield TSVs to minimize coupling Solved using MCF problem formulation Avenue for improvement Shield insertion cannot mitigate coupling if spacing is too small Determine signal and shield positions simultaneously 3/31/2014

Force-Driven Placement (FDP) Input: Fixed transistor placement Output: Placement for signal and shield TSVs Objective: place signal and shield TSVs Minimize some cost function Force: derivative of cost function Solution: find total force F=0 Iteratively solve for F=0 and then update forces based on new placement 3/31/2014

Forces Wirelength (WL) Force: pulls objects towards position with optimal wirelength Overlap Force: repels objects from one another when they overlap Coupling Force: repels each signal TSV from its most highly coupled neighbor Coupling evaluated using our geometric model Shielding Force: Pulls shield TSVs towards the signal TSVs it is assigned to 3/31/2014

Proposed Algorithm Assumption: Transistor cells are already placed, limiting the possible locations of TSVs (whitespace) Step 0: assign each signal TSV to a whitespace region Step 1: perform coupling aware placement until equilibrium Step 2: insert shields using our shield insertion method Step 3: repeat coupling aware placement until equilibrium 3/31/2014

Proposed Algorithm Assumption: Transistor cells are already placed, limiting the possible locations of TSVs (whitespace) Step 0: assign each signal TSV to a whitespace region Step 1: perform coupling aware placement until equilibrium Step 2: insert shields using our shield insertion method Step 3: repeat coupling aware placement until equilibrium WL force attracts TSVs back together Shield Reduces Coupling Force Coupling Force Repels TSVs 3/31/2014

Initial Placement Each signal TSV must be assigned to a whitespace region Once assigned TSVs cannot change regions Objective: Minimize wirelength Constrain #TSV assigned to each region 3/31/2014

Coupling Aware Placement Simulation Setup Four Cases Traditional Placement: WL and overlap force only Placement with coupling force (CA) Placement with shield insertion (SI) CA+SI Coupling Aware Placement Without With Shield Insertion Traditional CA SI CA+SI 3/31/2014

Experimental Results CA+SI required less shields than SI alone Improvement due to CA+SI is greater than the sum of CA and SI alone Change in total WL is an order of magnitude smaller than improvement to coupling 3/31/2014

Illustrative Example Coupling Unaware Coupling Aware Without Shields Traditional CA With Shields CA+SI SI 3/31/2014

Future Work We have shown that signal and shield TSV placement must be done simultaneously Also, coupling aware placement and shield insertion are complementary techniques This approach should be integrated with transistor placement Larger solution space No assumptions about TSV and transistor placement Optimize area Instead of adding a fixed amount of whitespace for TSVs during transistor placement 3/31/2014

Questions? 3/31/2014

Backup Slides 3/31/2014

Simulating Coupling S-parameter (S): ratio of energy inserted into one TSV to energy emitted by another Insertion loss, i.e. coupling ratio HFSS: Commercial FEM simulator of Maxwell’s equations HFSS data is used as golden data to construct model Our model is for specific physical dimensions. The modeling approach can be reapplied for different dimensions. 3/31/2014

Modeling Approach In HFSS: Model two signal TSVs Sweep distance d between them Add a shield Sweep d and shield distance y x value does not change results Add a second shield Sweep y1 and y2 Fit S(d,y1,y2) to HFSS data using curve fitting 3/31/2014

Modeling Approach In HFSS: Model two signal TSVs Sweep distance d between them Add a shield Sweep d and shield distance y x value does not change results Add a second shield Sweep y1 and y2 Fit S(d,y1,y2) to HFSS data using curve fitting 3/31/2014

Modeling Approach In HFSS: Model two signal TSVs Sweep distance d between them Add a shield Sweep d and shield distance y x value does not change results Add a second shield Sweep (x1,y1) and (x2,y2) Fit S(d,x1,y1,x2,y2) to HFSS data using curve fitting 3/31/2014

Modeling Approach In HFSS: Model two signal TSVs Sweep distance d between them Add a shield Sweep d and shield distance y x value does not change results Add a second shield Sweep (x1,y1) and (x2,y2) Fit S(d,x1,y1,x2,y2) to HFSS data using curve fitting 3/31/2014

Modeling Approach In HFSS: Model two signal TSVs Sweep distance d between them Add a shield Sweep d and shield distance y x value does not change results Add a second shield Sweep (x1,y1) and (x2,y2) Fit S(d,x1,y1,x2,y2) to HFSS data using curve fitting 3/31/2014

Extension and Validation Double shield model: Add results from single shield model: S(d,y1)+S(d,y2) Superposition is not an accurate model Subtract overlap M(x1,y1,x2,y2) Extension to n shields: Add results from single shield models: S(d,y1)+…+S(d,yn) Subtract overlap M(xi,yi,xj,yj) for each pair of shields Assumes higher order overlap is negligible Create random distributions of 3 and 4 shields Compare HFSS results to model results Average Error: S3: 3.7 % S4: 9.4 % S3: 1.6 dB S4: 4.6 dB 3/31/2014

Coupling Model 𝑆 0 (𝑑)=8.8× 1.035 −𝑑 −0.013𝑑−33.2 𝑆 𝑠 (𝑑,𝑦)=−( 𝑆 0 𝑑 +40.8)× 𝑏(𝑑) − 𝑦 𝑝(𝑑) 𝑏 𝑑 =71.08× 42.13 − 𝑑 0.21 +1 𝑝 𝑑 =0.013𝑑+0.44 𝑆 𝑛 𝑑, 𝑦 1 … 𝑦 𝑛 , 𝑥 1 … 𝑥 𝑛 = 𝑆 0 𝑑 + 𝑖=1 𝑛 𝑆 𝑠 𝑑, 𝑦 𝑖 − 𝑗=1 𝑖−1 𝑀( 𝑦 𝑖 , 𝑦 𝑗 , 𝑥 𝑖 , 𝑥 𝑗 ) 𝑀 𝑦 𝑖 , 𝑦 𝑗 , 𝑥 𝑖 , 𝑥 𝑗 = 𝑀 0 ( 𝑦 𝑖 , 𝑦 𝑗 )× 1.137 − 𝑑𝑖𝑠𝑡( 𝑦 𝑖 , 𝑦 𝑗 , 𝑥 𝑖 , 𝑥 𝑗 ) 0.563 𝑀 0 𝑦 𝑖 , 𝑦 𝑗 =−3.09× 1.0001 − 𝑦 𝑖 1.82 + 1.0001 − 𝑦 𝑗 1.82 3/31/2014

Shield Insertion Algorithm [Serafy et. al GLSVLSI’13] For each signal TSV pair we identify the region where a shield could improve the coupling of that pair Assign a shield to each TSV pair using MCF problem formulation Objective: provide shielding for each TSV pair while using least number of shields Take advantage of region overlap Poor Solution Good Solution 3/31/2014

MCF Shield Insertion Algorithm From Serafy et. al GLSVLSI’13 Each pair of signal TSVs defines a region A set of positions that are good candidates for shielding that pair MCF problem: assigns a shield to each TSV pair Objective: Maximize ratio of shielding added to shielding required (shielding ratio) for each TSV pair while using least number of shields 3/31/2014

MCF Problem Formulation From Serafy et. al GLSVLSI’13 Region node for each TSV pair Point node for each whitespace grid point Point cost proportional to total shielding ratio True cost of each shield is independent of amount of flow carried u = capacity c = cost Heuristic: After each iteration scale cost by number of units of flow carried in previous iteration 3/31/2014

Placement Forces FKOZ is the overlap force FWL is the wirelength force Prevents a TSV from getting within the KOZ area of a transistor or another TSV FWL is the wirelength force Pushes each TSV towards its respective netbox TSVs inside the netbox have minimal WL and FWL = 0 FC is a new force which captures the coupling between two TSVs Coupling force is proportional to the coupling between two TSVs Each TSV has a coupling force from all other TSVs, but only the strongest coupling force is used to determine movement on each iteration FShielding pushes shield TSVs towards each signal TSV they are assigned to A: all signal TSVs assigned to this shield 3/31/2014

Why max(Fc) Don’t let many loosely coupled TSVs overpower strongly coupled TSV 3/31/2014

Raw Data Traditional CA SI CA+SI B1 -25.0 -25.3 -25.2 -26.2 B2 -25.5 -26.1 -26.5 B3 -26.4 B4 -25.6 B5 -26.3 B6 B7 -25.7 -25.4 B8 AVG -25.8 3/31/2014

Improvement (dB) CA SI CA+SI B1 -0.3 -0.1 -1.1 B2 -0.2 -0.8 -1.2 B3 0.0 -0.7 B4 0.1 B5 -0.9 -1.0 B6 B7 -0.4 B8 AVG -0.5 3/31/2014