RAPID Memory Compiler Evaluation by David Artz Oracle Labs November 2011

Overview of <Vendor A> SRAM/RF Compilers <Insert Picture Here> A competitive assessment against TSMC memory compilers is not available at this time as we are still waiting on legal access to said technology. Features: Speed and/or high density Aspect ratio control for floor planning Memory operation and retention at low frequency Low active power and leakage-only standby power Views/models Extra Margin Adjustment (EMA) Soft Error Repair (SER) Redundancy Over-the-cell power routing Maximum static power dissipation corner Power gating Pipeline register Advanced Test Feature (ATF)

Speed and/or High Density

Aspect Ratio Control for Floor Planning Note: Memories must be rotated ± 90°for poly orientation rule

Memory Operation and Retention at Low Frequency Before going into retention mode, the memory needs to be in standby mode by setting CEN =1. The CLK pin must be held low before a high or low transition of RET1N, in accordance with the timing arcs specified in the Liberty model. Once this is accomplished, set RET1N=0. The power is still supplied to the memory core and the periphery. The word lines are clamped low. VDDPE can now be shut down and VDDCE may be varied within the limits required in Power gating compiler manual.

Views/Models

Extra Margin Adjustment (EMA) Extra margin adjustment pins provide the option of adding delays into internal timing pulses. There are three sets of EMA pins: EMA[2:0], EMAS, EMAW[1:0]. Use of the EMA[2:0] pins provides extra time for memory read and write operations by slowing down the memory access. There are three input pins, named EMA[2], EMA[1], EMA[0], for each instance. The access time and cycle times are progressively increased as the pins are driven from 000 to 111 respectively. The EMA[2:0] pins are always visible. Margin sequentially increases as EMA sequentially increments from 000 through 111. Setting 000 is the fastest setting and 111 is the slowest setting. Minimum EMA setting for given operating range is documented in the model .lib file. When enabled, the EMAS pin extends the pulse width of the sense-amp enable signal. The default setting is low but when driven high the pulse is extended. The setting on this pin does not affect the access time, but it will affect cycle time in the read cycle. When enabled, the EMAW[1:0] pins add delay for write cycles. They do not affect the access and cycle time during read operation (GWEN=1). The write access and cycle time is the sum of EMA[2:0] and EMAW[1:0].

Over The Cell Power Routing You must route chip-level ground (VSS) and VDD to the memory instance and drop vias down to the m4 straps. In order to maintain power density for each strap, use multiple top-level grid connections with a maximum spacing of 15um and a minimum width to provide coverage for a via array count of three. The top supply metal in SRAM compilers is m4. To meet instance IR drop requirements, m5 straps at least 0.21um wide for VDDPE, VSSE, and VDDCE must be located over the instance, perpendicular to the instance m4 supply strap direction, and within 10um of the instance edge. In addition, a pattern of VDDPE, VSSE, and VDDCE m5 straps, each at least 0.21um wide, must be repeated across the instance at 15um intervals. Each intersection of instance supply m4 and overlapping, perpendicular supply strap m5 should be maximally contacted.

Power Gating

Power Gating (cont). Note: the additional power gating modes come at an extreme cost in performance for all power saving states (i.e., ~ 200 clock cycles to negotiate retention modes) Note: We can implement our own power down via header switches B1 B2 B3 B4 B5 B1 B2 B3 B4 B5