Basic Microprocessor Timing ECE 611 Microprocessor Systems Dr. Roger L. Haggard, Associate Professor Department of Electrical and Computer Engineering Tennessee Technological University Spring 1998 RLH - Spring 1998

68000 Bus Timing - Read States Mem/IO Read (Slow) Mem/IO Read Bus Cycle Bus Cycle S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 W W W W S5 S6 S7 CLK Valid A(23 -1) Data In Data In D(15 - 0) Addr Valid AS* Enable Data In LDS* UDS* Read R/W Ready W DTACK* (Must Rise) RLH - Fall 1997RLH - Spring 1998

68000 Bus Timing - Write Mem/IO Write (Slow) Mem/IO Write Bus Cycle CLK Valid A(23 -1) Data Out D(15 - 0) Addr Valid AS* Latch Data LDS* UDS* Write Enable R/W Ready W DTACK* RLH - Fall 1997RLH - Spring 1998

8086 Bus Timing - Read Two Wait States States Mem Read I/O Input Bus Cycle Bus Cycle T1 T2 T3 T4 T1 T2 T3 Tw Tw T4 CLK Status A,BHE A(19-16) BHE A Data In AD(15-0) Latch Address ALE Mem I/O M / IO Read RD Receive DT/R Disable Enable DEN Ready Wait READY Valid AB(19-0) Data In DB(15-0) RLH - Fall 1997RLH - Spring 1998 (WR is kept high)

8086 Bus Timing - Write One Wait State Mem Write I/O Output Bus Cycle Tw T4 CLK Status A,BHE A(19-16) BHE AD(15-0) Data Out A Latch Address ALE Mem I/O M / IO Write WR Latch Data Transmit DT/R Disable Enable DEN Ready Wait READY Valid AB(19-0) Data Out DB(15-0) RLH - Fall 1997RLH - Spring 1998 (RD is kept high)

8051 Timing - Program Memory Read Machine Cycle XTAL2 S1 S2 S3 S4 S5 S6 ALE PSEN Enable In A[7-0] out Port 0 / AD[7-0] D[7-0] in A[15-8] Byte1 Port 2 / Byte2 (if needed) RLH - Fall 1997RLH - Spring 1998

8051 Timing - Data Memory Read P1 P2 Machine Cycle 1 XTAL2 S1 S2 S3 S4 S5 S6 Machine Cycle 2 ALE PSEN Read Inst RD Read Data (data) (inst) A[7-0] out Port 0 / AD[7-0] D[7-0] in A[15-8] Port 2 / (data) (inst) RLH - Fall 1997RLH - Spring 1998

8051 Timing - Data Memory Write P1 P2 Machine Cycle 1 XTAL2 S1 S2 S3 S4 S5 S6 Machine Cycle 2 ALE PSEN Read Inst WR Write Data A[7-0] out Port 0 / AD[7-0] D[7-0] in (data) (inst) A[15-8] Port 2 / (data) (inst) RLH - Fall 1997RLH - Spring 1998

Memory Interfacing and Timing RLH - Spring 1998

Interface 68000 to 6116 static RAM (1) 6116 (2K x8) 16 A(10-0) Address bus Data bus D00- D07 D(7-0) Lower byte A01-A11 RAM1 68000 CPU A(10-0) D08- D15 D(7-0) Upper byte D00- D15 RAM2 RLH - Fall 1997RLH - Spring 1998

Interface 68000 to 6116 static RAM (2) AS* R/W Low in a write cycle when AS* also low OE* R/W RAMCS* low when RAM1 or RAM2 addressed CS2* LDS* UDS* A12- A23 Address decoder CS1* Low during access to RAM2 when UDS* low Low during access to RAM1 when LDS* low 6116 (2K x8) CS* RAM1 68000 CPU R/W OE* CS* RAM2 DTACK* DTACK Gen Low when either RAM1 or RAM2 selected delays DTACK* to introduce wait states RLH - Fall 1997RLH - Spring 1998

Interface 8086 to 6116 static RAM 20 Latch Addr Decoder A(11-1) 21 A0, BHE* A(19-12) 8086 6116 (2K x8) A(10-0) A ____ BHE D(7-0) D(7-0) D(15-8) 16 __ R/W low byte (even) ALE OE* D CS* A0 RAMCS* MEM* BHE* A(10-0) __ M/IO D(7-0) __ R/W hi byte (odd) ___ WR ___ RD OE* CS* Wait State Gen READY RLH - Fall 1997RLH - Spring 1998