ES Seminar1 Communicating Transaction Processes P.S. Thiagarajan National University of Singapore Joint Work with: Abhik Roychoudhury; ……

ES Seminar2 The Main Features To support System Level Design –One Level of Abstraction higher than C, C++, VHDL.. UML-compatible –MSCS + Asynchronous control flow –Based on MSCs (Message Sequence Charts) –Sequence Diagrams

ES Seminar3 Why System Level Design? Closer to end-use(r). Less detailed and more architecture-neutral. Easier reuse/adaptaton. Easier to verify. –Safety-critical applications need to be correct. –Catch design errors early. –Coupling with a correct-by-construction synthesis method is an attractive option.

ES Seminar4 What is Available? Data flow graphs. Automata of various kinds. Petri nets. State charts. Esterel, Lustre. SDL, UML.

ES Seminar5 Why UML-compatible? UML is getting rapidly established as a standard. –Mainly in software engineering projects –Increasingly so in embedded systems domain. Offers a suite of graphical notations: –Multiple views –Behavioral and structural diagrams. –Object orientation.  Reuse, adaptation

ES Seminar6 An Idealized Design Flow Requirements Exec. Specifications. Intermediate representation SW/HW Implementation. High Level Description

ES Seminar7 Requirements and Exec. Specifications Requirements : Message Sequence Charts (MSCs) Exec. Specifications : –State charts. UML supports both but no clear distinction made. Other Exec. Spec. : –Petri nets, –MPAs (Message Passing Automata), ….

ES Seminar8 MSCs Message Sequence Charts: –Describe scenarios. –A finite pattern of interaction between agents (object instances,..). –A story

ES Seminar9 Message Sequence Charts rq U1R rq y n U2

ES Seminar10 Message Sequence Charts rq U1R rq y n U2

ES Seminar11 Message Sequence Charts rq U1R rq y n U2 internal action

ES Seminar12 Message Sequence Charts rq U1R rq y n U2 internal actions

ES Seminar13 Message Sequence Charts rq U1R rq y n U2

ES Seminar14 Message Sequence Charts rq U1R rq y n U2

ES Seminar15 Message Sequence Charts rq U1R rq y n U2

ES Seminar16 Message Sequence Charts rq U1R rq y n U2

ES Seminar17 Message Sequence Charts rq U1R rq y n U2

ES Seminar18 Message Sequence Charts rq U1R rq yn U2

ES Seminar19 Message Sequence Charts rq U1R rq y n U2

ES Seminar20 Message Sequence Charts rq U1R rq y n U2

ES Seminar21 Message Sequence Charts rq U1R rq y n U2

ES Seminar22 CTPs Communicating Transaction Processes. An executable spec. mechanism. –Based on MSCs. A network of interacting agents. –Agent’s interaction pattern behavior:  Standard distributed system model –Interaction:  Guarded choice of MSCs.  Transaction schemes.

ES Seminar23 Distributed System Models Petri nets Data flow graphs Statecharts Distributed transition systems (many kinds!) Process algebras (CCS, CSP, …)

ES Seminar24 PI1 IB1IB2 PI2 I1 B I2 P2

ES Seminar25 PI1 IB1IB2 PI2 I1 B I2 P2

ES Seminar26 PI1 IB1IB2 PI2 I1 B I2 P2

ES Seminar27 PI1 IB1IB2 PI2 I1 B I2 P2

ES Seminar28 PI1 IB1IB2 PI2 I1 B I2 P2

ES Seminar29 PI1 IB1IB2 PI2 I1 B I2 P2 But the boxes will have internal structure. A complex Transaction Scheme.

ES Seminar30 Transaction Scheme waitcount2:= waitcount2 + 1  2data.present & B.free  2data.present &  B.free  I2B req y add data I2B req n I2B   2data.present 

ES Seminar31 PI1 IB1IB2 PI2 I1 B I2 req y add data  2data.present & B.free 

ES Seminar32 PI1 IB1IB2 PI2 I1 B I2 req y add data  2data.present & B.free  

ES Seminar33 PI1 IB1IB2 PI2 I1 B I2 req y add data  2data.present & B.free  

ES Seminar34 PI1 IB1IB2 PI2 I1 B I2 req y add data  2data.present & B.free  

ES Seminar35 PI1 IB1IB2 PI2 I1 B I2 req y add data  2data.present & B.free  

ES Seminar36 PI1 IB1IB2 PI2 I1 B I2 req y add data  2data.present & B.free  

ES Seminar37 PI1 IB1IB2 PI2 I1 B I2 req y add data  2data.present & B.free  

ES Seminar38 P11 I1  1data.present  no-op  1data.present   1data.present  no-data  1data.present  data  1data.present  P11 Transaction Scheme I1

ES Seminar39 Analysis Issues Determine whether a CTP is bounded. Determine if a CTP can deadlock. Determine if a CTP is well-formed.

Current Status The CTP Model SMV ES Representation Verilog Analysis Verification Simulation; Synthesis Case Studies Modeling

Current Status The CTP Model SMV ES Representation Verilog Analysis Verification Simulation; Synthesis Case Studies Modeling Pankaj Jain Nikhil Jain Kamrul Hasan Talukdar Tran Tuan Anh Ge Zhiguo

ES Seminar42 Future Work Add multiple instances of a process. –Object features Add timing constraints. Develop the computational model. –Interactions with environment (sense, actuate) –Computational steps (control law) –Schedulability is a key issue. HW/SW Partitioning; Architectural mapping; Synthesis?