Encoders Module M9.3 Section 6.3. Encoders Priority Encoders TTL Encoders.

Slides:

Advertisements

Similar presentations

Adders Module M8.1 Section 6.2. Adders Half Adder Full Adder TTL Adder.

Advertisements

1 The 2-to-4 decoder is a block which decodes the 2-bit binary inputs and produces four output All but one outputs are zero One output corresponding to.

Modulo-N Counters Module M10.4 Section 7.2.

5.5 Encoders A encoder is a multiple-input, multiple-output logic circuit that converts coded inputs into coded outputs, where the input and output codes.

Demultiplexers Module M6.4 Section 6.4. Demultiplexers YIN 1 x 4 DeMUX d0d1 Y0 Y1 Y2 Y3 Y0 Y1 Y2 Y3 d1d0 0 0 YIN YIN YIN

Shift Registers Module M11.1 Section 7.3.

7-Segment Displays Lecture L6.1 Section 6.3. Turning on an LED.

Memory Section 7.2. Types of Memories Definitions – Write: store new information into memory – Read: transfer stored information out of memory Random-Access.

Magnitude Comparator Lecture L6.4 Section 6.1.

Binary Counters Module M10.3 Section 7.2. Counters 3-Bit Up Counter 3-Bit Down Counter Up-Down Counter.

7-Segment Displays Lecture L6.7 Section 6.5. Turning on an LED.

Binary-to-BCD Converter Lecture L6.2 Section 6.5 pp

Using State Machines as Control Circuits Lecture L9.4.

Multiplier Lecture L7.3 Section 10.4 (p.276) Section 7.3 (Handout)

1 CS 140 Lecture 12 Standard Combinational Modules Professor CK Cheng CSE Dept. UC San Diego.

Multiplexers Lecture L6.4 Section 6.4.

CS 140 Lecture 11 Professor CK Cheng 5/09/02. Part III - Standard Modules Decoder, Encoder, Mux, DeMux, Shifter, Adder, Multiplexer Interconnect: Decoder,

Subtractors Module M8.2 Section 6.2. Subtractors Half Subtractor Full Subtractor Adder/Subtractor - 1 Adder/Subtractor - 2.

Designing State Machines Lecture L9.2 Handout Section 9.2.

Arbitrary Waveforms Lecture L8.5 Section 7.2. CLK DQ !Q CLK DQ !Q CLK DQ !Q Q0Q0.D Q1 Q2 Q1.D Q2.D s s s s3 0 1.

Counters as State Machines Lecture L9.1 Handout Section 9.1.

Designing State Machines SQRT controller Lecture L9.2a Section 9.2.

Equality Detector Lecture L6.1 Section 6.1. Equality Detector XNOR X Y Z Z = !(X $ Y) X Y Z

Flip-Flops Module M10.2 Section 7.1. D Latch Q !Q CLK D !S !R S R X 0 Q 0 !Q 0 D CLK Q !Q Note that Q follows D when the clock in high, and.

Binary Counters Lecture L8.3 Section 8.2. Counters 3-Bit Up Counter 3-Bit Down Counter Up-Down Counter.

Shifter Lecture L7.4 Group HW #4 Section 10.3.

Modulo-N Counters Lecture L8.4 Section 7.2. Counters Modulo-5 Counter 3-Bit Down Counter with Load and Timeout Modulo-N Down Counter.

Codes and Code Converters

Communicating With Devices Interrupts Lecture 10.4 Section 10.6.

Code Converters Module M7.1 Section 6.5. Code Converters Binary-to-BCD Converters ABEL TRUTH_TABLE Command.

CS 140 Lecture 12 Professor CK Cheng 11/07/02. Part III - Standard Modules Decoder, Encoder, Mux, DeMux, Shifter, Adder, Multiplexer Interconnect: Decoder,

Arbitrary Waveforms Module M10.5 Section 7.2. CLK DQ !Q CLK DQ !Q CLK DQ !Q Q0Q0.D Q1 Q2 Q1.D Q2.D s s s s3 0 1.

Arithmetic Logic Unit (ALU) Lecture L7.5 Section 7.5.

Pulse-Width Modulated DAC Lecture 11.3 Section 11.5.

Multiplexers Module M6.1 Section 6.4. Multiplexers A 4-to-1 MUX TTL Multiplexer A 2-to-1 MUX.

2’s Complement 4-Bit Saturator

Adders Lecture L7.1 Section 6.2 Section 10.4 (pp )

Shifters Lecture L7.4 Section 7.4. MODULE shift TITLE 'shifter' DECLARATIONS " INPUT PINS " D3..D0 PIN 11,7,6,5; D = [D3..D0]; s2..s0 PIN 3,2,1; S.

Flip-Flops Lecture L8.2 Section 8.1. Recall the !S-!R Latch !S !R Q !Q !S !R Q !Q X Y nand 1 0 Set 1 0.

Decoders Module M9.1 Section 6.3. Decoders TTL Decoders.

Arithmetic Logic Unit (ALU) Lecture L9.3 Lab 10. ALU CB = carry_borrow flag Z = zero flag (Z = 1 if Y = 0)

Shift Registers Lecture L6.6 Section Bit Shift Register.

Equality Detector Lecture L6.3 Section 6.1. Equality Detector XNOR X Y Z Z = !(X $ Y) X Y Z

Decoders and Encoders Sections 3-5, 3-6 Mano & Kime.

7-Segment Displays Module M7.2 Section 6.5. Turning on an LED Common Anode.

Flip-Flops Lecture L8.2 Section 7.1 – Book Sect. 8.1– Handout.

OTHER COMBINATIONAL LOGIC CIRCUITS WEEK 7 AND WEEK 8 (LECTURE 2 OF 3)

Multiplexers Lecture L6.6v Section 6.2. Multiplexers A Digital Switch A 2-to-1 MUX A 4-to-1 MUX A Quad 2-to-1 MUX The Verilog if…else Statement TTL Multiplexer.

Address Decoders Lecture L6.10 Section 6.3. MOUSE Layout PROM 2716 RAM 6810 MPU 6802 PIA 6821 Address Bus (16 lines) Data Bus (8 lines) To outside world.

Decoders and Encoders Discussion D4.2. Decoders and Encoders Binary Decoders Binary Encoders Priority Encoders.

1 Digital Logic Design Week 7 Decoders, encoders and multiplexers.

Lecture # 11 University of Tehran

9/15/09 - L15 Decoders, Multiplexers Copyright Joanne DeGroat, ECE, OSU1 Decoders and Multiplexer Circuits.

Lab 6 Module M8.3. EXPERIMENT 6: Adder/Subtractor PRE-LAB 1.Read and understand text Sec. 6.2, Adders and Subtractors, pages Using textbook.

Printer Port * 0= * 1= * 6= 60 1 * 4 = 4 = 164 Decimal Binary We use Ten Symbols

Dept. of Electrical and Computer Eng., NCTU 1 Lab 4. BCD Adder Presenter: Chun-Hsien Ko Contributors: Chung-Ting Jiang and Lin-Kai Chiu.

Digital Design Lecture 8 Combinatorial Logic (Continued)

AND Gate Inputs Output Input A (Switch) Input B (Switch) Output Y (Lamp) 0 (Open) 0 (OFF) A B Lamp.

Boolsk algebra. Logiske funktioner i Peel PEEL 18CV8 logic diagram.

Tutorial 9 Module 8 – 8.1,8.2,8.3. Question 1 Distinguish between vectored and non-vectored interrupts with an example Build a hardware circuit that can.

Encoders The inverse function of a decoder. Priority Encoder resolve the ambiguity of illegal inputs only one of the input is encoded D 3 has the highest.

Magnitude Comparator Module M5.2 Section 6.1.

Dept. of Electrical and Computer Eng., NCTU

(74LS47)BCD-to-Seven Decoder and 7 Segment Display

Counters as State Machines

Shift Registers Lecture L8.6 Section 8.3.

Data Distribution Board

Magnitude Comparator Lecture L6.2 Section 6.1.

Combinational circuits design

Presentation transcript:

Encoders Module M9.3 Section 6.3

Encoders Priority Encoders TTL Encoders

Encoders A B I0 I1 I2 I3 4-to-2 Encoder I0 I1 I2 I3 B A

Encoders I0 I1 I2 I3 B A Assume only 1 input can be high at any time. A = I1 # I3 B = I2 # I3 I1 I2 I3 I0 B = I2 # I3 A = I1 # I3

8-to-3 Encoder I0 I1 I2 I3 I4 I5 I6 I7 Y2 Y1 Y0 Y2 = I7 # I6 # I5 # I4 Y1 = I7 # I6 # I3 # I2 Y0 = I7 # I5 # I3 # I1

encoder.abl MODULE encoder83 TITLE 'Encoder, D. Hanna, 7/15/02' DECLARATIONS " INPUT PINS " I7..I0 PIN 6, 7, 11, 5, 72, 71, 66, 70; " Switch 1..8 " OUTPUT PINS " Y2..Y0 PIN 37, 36, 35 ISTYPE 'com'; " LED 6..8 EQUATIONS Y2 = I7 # I6 # I5 # I4; Y1 = I7 # I6 # I3 # I2; Y0 = I7 # I5 # I3 # I1; END encoder83

Priority Encoder X X X X X X X X X X X X X X X X X X X X X X X X X X X X I0 I1 I2 I3 I4 I5 I6 I7 Y2 Y1 Y0

Priority Encoder X X X X X X X X X X X X X X X X X X X X X X X X X X X X I0 I1 I2 I3 I4 I5 I6 I7 Y2 Y1 Y0 Y2 = L7 # L6 # L5 # L4 L7 = I7 L6 = !I7 & I6 L5 = !I7 & !I6 & I5 L4 = !I7 & !I6 & !I5 & I4

Priority Encoder X X X X X X X X X X X X X X X X X X X X X X X X X X X X I0 I1 I2 I3 I4 I5 I6 I7 Y2 Y1 Y0 Y1 = L7 # L6 # L3 # L2 L7 = I7 L6 = !I7 & I6 L3 = !I7 & !I6 & !I5 & !I4 & I3 L2 = !I7 & !I6 & !I5 & !I4 & !I3 & I2

Priority Encoder X X X X X X X X X X X X X X X X X X X X X X X X X X X X I0 I1 I2 I3 I4 I5 I6 I7 Y2 Y1 Y0 Y0 = L7 # L5 # L3 # L1 L7 = I7 L5 = !I7 & !I6 & I5 L3 = !I7 & !I6 & !I5 & !I4 & I3 L1 = !I7 & !I6 & !I5 & !I4 & !I3 & !I2 & I1

pencoder.abl MODULE pencoder83 TITLE 'Priority Encoder, A. Student, 7/15/02' DECLARATIONS " INPUT PINS " I7..I0 PIN 6, 7, 11, 5, 72, 71, 66, 70; " Switch 1..8 " OUTPUT PINS " Y2..Y0 PIN 37, 36, 35 ISTYPE 'com'; " LED 6..8 VALID PIN 44;" LED 1 " VALID = 1 for valid binary output " INTERMEDIATE NODES " L7..L0 NODE ISTYPE 'com'; " internal vector

pencoder.abl (cont’d) EQUATIONS L7 = I7; L6 = !I7 & I6; L5 = !I7 & !I6 & I5; L4 = !I7 & !I6 & !I5 & I4; L3 = !I7 & !I6 & !I5 & !I4 & I3; L2 = !I7 & !I6 & !I5 & !I4 & !I3 & I2; L1 = !I7 & !I6 & !I5 & !I4 & !I3 & !I2 & I1; Y2 = L7 # L6 # L5 # L4; Y1 = L7 # L6 # L3 # L2; Y0 = L7 # L5 # L3 # L1; END pencoder83

TTL Encoder GND Vcc A2 A1 E1 E0 GS 0 A0 74LS148 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X EI A2 A1 A0 GS EO Priority Encoder

68000 Interrupt Logic Peripheral Encoder Decoder IP0 IP1 IP2 A0 A1 A2 IRQA Data Bus IRQ