Encoders Three-state devices Multiplexers ECE 3110: Introduction to Digital Systems Chapter 5 Combinational Logic Design Practices Encoders Three-state devices Multiplexers

74x138/139 decoders

Encoders Multiple-input/multiple-output device. Perfoms the inverse function of a Decoder. Outputs ( m ) are less than inputs ( n ). Converts input code words into output code words. input code output code ENCODER

Encoders vs. Decoders Binary decoders/encoders Decoder Encoder n-to-2^n Input code : Binary Code Output code :1-out-of-2^n. 2^n-to-n encoder Input code : 1-out-of-2^n. Output code : Binary Code

Binary Encoder 2^n-to-n encoder : 2^n inputs and n outputs. Input code : 1-out-of-2^n. Output code : Binary Code Example : n=3, 8-to-3 encoder Inputs Outputs I0 I1 I2 I3 I4 I5 I6 I7 Y0 Y1 Y2 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 1 1 1 1 I4 Y2 I5 I6 I7

8-to-3 encoder Implementation Simplified implementation: - From the truth table Y2 = I1 + I3 + I5 + I7 Y1 = I2 + I3 + I6 + I7 Y0 = I4 + I5 + I6 + I7 Limitations : - I0 has no effect on the output - Only one input can be activated Application: Handling multiple devices requests But, no simultaneous requests Establishing priorities solve the problem of multiple requests Y0 I1 I2 Y1 I3 I4 I5 Y2 I6 I7

Need priority in most applications

Priority Encoder Assign priorities to the inputs When more than one input are asserted, the output generates the code of the input with the highest priority Priority Encoder : H7=I7 (Highest Priority) H6=I6.I7’ H5=I5.I6’.I7’ H4=I4.I5’.I6’.I7’ H3=I3.I4’.I5’.I6’.I7’ H2=I2.I3’.I4’.I5’.I6’.I7’ H1=I1. I2’.I3’.I4’.I5’.I6’.I7’ H0=I0.I1’. I2’.I3’.I4’.I5’.I6’.I7’ IDLE= I0’.I1’. I2’.I3’.I4’.I5’.I6’.I7’ - Encoder Y0 = H1 + H3 + H5 + H7 Y1 = H2 + H3 + H6 + H7 Y2 = H4 + H5 + H6 + H7 Priority encoder Priority Circuit Binary encoder I7 I7 H7 I7 I6 I6 H6 I6 I5 I5 H5 I5 Y2 A2 I4 I4 H4 I4 Y1 A1 I3 I3 H3 I3 Y0 A0 I2 I2 H2 I2 I1 I1 H1 I1 I0 I0 H0 I0 IDLE IDLE

8-input priority encoder I7 has the highest priority,I0 least A2-A0 contain the number of the highest-priority asserted input if any. IDLE is asserted if no inputs are asserted.

74x148 8-input priority encoder Active-low I/O Enable Input “Got Something”:Group Select Enable Output

74x148 Truth Table

74x148 circuit

Cascading priority encoders 32-input priority encoder

Three State Buffers/Drivers A buffer/inverter with enable input Buffer Buffer Inverter Inverter Actice High Enable Actice Low Enable Active High Enable Actice Low Enable The device behaves like an ordinary buffer/inverter when the enable input is asserted. The ouput is floating ( High Impedance, Hi-Z ) when the enable input is deasserted ( The input is isolated from the output, behaves as if it did not exist) Application: Controlling the access of a single line/bus by multiple devices

Three-state buffers Output = LOW, HIGH, or Hi-Z. Can tie multiple outputs together, if at most one at a time is driven.

8 sources share a three-state party line

Timing considerations

Standard SSI/MSI 3-state buffers SSI: 74x125, 74x126 (independent enable inputs) MSI: 74x541 and varieties such as 74x540, 74x240, 74x241

Octal noninverting 3-state buffer Hysteresis

Driver application

Three-state transceiver Pairs of 3-state buffers connected in opposite directions between each pair of pins, so data can be transferred in either direction. DIR determines the direction of transfer (A-->B or B-->A)

Transceiver application Bidirectional buses

Multiplexers (mux) Eg. Put between Processor’s registers and ALU A 16-bit processor where 3-bit field specifies on of 8 registers. The 3-bit field is connected to the select inputs of an 8-input, 16-bit mux. Select one of n sources of data to transmit on a bus.

MSI: 74x151 8-input 1-bit multiplexer

74x151 truth table

Other multiplexer varieties 2-input, 4-bit-wide 74x157 4-input, 2-bit-wide 74x153

Expanding Multiplexers 32-to-1 mux

Demultiplexers A mux is used to select one of n sources of data to transmit on a bus. A demultiplexer can be used to route the bus data to one of m destinations. Just the inverse of a mux. A binary decoder with an enable input can be used as a demux. Eg. 74x139 can be used as a 2-bit, 4-output demux.

Next… X-OR gates and Parity circuits Comparators Adders, subtractors, ALUs Reading Wakerly CH-5.8-5.11