GCT Meeting: DTPM Status: Greg Iles1 July 20051 DTPM Fundamentals TPMs 0 to 7 send event data and status and receive control Receive TPM event data Buffer.

Slides:

Advertisements

Similar presentations

GCT Source Card Status John Jones Imperial College London

Advertisements

GCT Software ESR - 10th May 2006 Jim Brooke. Jim Brooke, 10 th May 2006 HAL/CAEN Overview GCT Driver GCT GUI Trigger Supervisor Config DB Test scripts.

Internal Logic Analyzer Final presentation-part B

Internal Logic Analyzer Final presentation-part A

Autonomous Helicopter: James Lyden Harris Okazaki EE 496 A project to create a system that would allow a remote- controlled helicopter to fly without user.

M.J. LeVine1STAR HFT meeting, Sept 27-28, 2011 STAR SSD readout upgrade M. LeVine, R. Scheetz -- BNL Ch. Renard, S. Bouvier -- Subatech J. Thomas -- LBNL.

Trigger System Functions Master/Slave Operation –Located in Readout Boards’ BE-FPGA, but only active as Master in one slot. –Master controls asynchronous.

Data Communication and Networks Lecture 2 ADTs in Protocol Design (Ring Buffer, Queue, FSM) September 16, 2004 Joseph Conron Computer Science Department.

1 Design For Debug Using DAFCA system Gadi Glikberg 15/6/06.

Uli Schäfer 1 JEM1: Status and plans power Jet Sum R S T U VME CC RM ACE CAN Flash TTC JEM1.0 status JEM1.1 Plans.

E-Voting Machine - Design Presentation Group M1 Jessica Kim Chi Ho Yoon Jonathan Chiang Donald Cober Mon. Sept 8 Initial Design Secure Electronic Voting.

1 States report for readout system 1.PHENIX readout system overview 2.High speed data link 3.Digital pilot ASIC 4.Schedule Hiroyuki

Final presentation – part B Olga Liberman and Yoav Shvartz Advisor: Moshe Porian April 2013 S YMBOL G ENERATOR 2 semester project.

SBS/A1n DAQ status Alexandre Camsonne August 28 th 2012.

U N C L A S S I F I E D FVTX Detector Readout Concept S. Butsyk For LANL P-25 group.

Chapter 6 – Connectivity Devices

Verification Plan & Levels of Verification

Status of the Beam Phase and Intensity Monitor for LHCb Richard Jacobsson Zbigniew Guzik Federico Alessio TFC Team: Motivation Aims Overview of the board.

1 Programming of FPGA in LiCAS ADC for Continuous Data Readout Week 3 Report Jack Hickish.

Status of Global Trigger Global Muon Trigger Sept 2001 Vienna CMS-group presented by A.Taurok.

Electronic System Design GroupInstrumentation DepartmentRob Halsall et al.Rutherford Appleton Laboratory21 October 2002 CMS Tracker FED Back End FPGA Frame_Sync_out0.

LZRW3 Data Compression Core Dual semester project April 2013 Project part A final presentation Shahar Zuta Netanel Yamin Advisor: Moshe porian.

Bernardo Mota (CERN PH/ED) 17/05/04ALICE TPC Meeting Progress on the RCU Prototyping Bernardo Mota CERN PH/ED Overview Architecture Trigger and Clock Distribution.

Instrumentation DepartmentCCLRC Rutherford Appleton Laboratory28 March 2003 FED Project Plan 2003 FED Project aiming to satisfy 2 demands/timescales: Module.

FED RAL: Greg Iles5 March The 96 Channel FED Tester What needs to be tested ? Requirements for 96 channel tester ? Baseline design Functionality.

PROJECT - ZYNQ Yakir Peretz Idan Homri Semester - winter 2014 Duration - one semester.

Acquisition Crate Design BI Technical Board 26 August 2011 Beam Loss Monitoring Section William Vigano’ 26 August

FPGA firmware of DC5 FEE. Outline List of issue Data loss issue Command error issue (DCM to FEM) Command lost issue (PC with USB connection to GANDALF)

1 Programming of FPGA in LiCAS ADC for Continuous Data Readout Week 5 Report Tuesday 29 th July 2008 Jack Hickish.

Instrumentation DepartmentCCLRC Rutherford Appleton Laboratory Clocks Data FEDv1 Final Firmware Subtasks Serial Comms VME LINK VME Bus VME SystemACE System.

Trigger Meeting: Greg Iles5 March The APV Emulator (APVE) Task 1. –The APV25 has a 10 event buffer in de-convolution mode. –Readout of an event =

Part A Final Dor Obstbaum Kami Elbaz Advisor: Moshe Porian August 2012 FPGA S ETTING U SING F LASH.

SRS Activities at IFIN-HH: VMM2 Hybrid, FECv6 Firmware, High- Density Optical ATCA-SRS Mezzanine Sorin Martoiu, Michele Renda, Paul Vartolomei (IFIN-HH.

Agata Week – LNL 14 November 2007 LLP ATCA Carrier Status M. Bellato on behalf of the LLP Carrier Working Group.

Proposal for an Open Source Flash Failure Analysis Platform (FLAP) By Michael Tomer, Cory Shirts, SzeHsiang Harper, Jake Johns

Bottom half – ch 0-5 placed & routed FE PS PROC FIFO TRIG OSC RX/SHAP ADC DAC VME.

Trigger matched firmware Top Level block diagram 4ch 3.2gbps deserializer “Test Assembly 1” Module Latency buffer 1GB DDR2 DRAM a.c.r The GTKRO.

S. Durkin, CMS EMU Meeting U.C. Davis Feb. 25, DMB Production 8-layer PC Board, 2 Ball-Grid Array FPGA’s, 718 Components/Board 550 Production Boards.

1 MICE Tracker Readout Update Introduction/Overview TriP-t hardware tests AFE IIt firmware development VLSB firmware development Hardware progress Summary.

Trigger Workshop: Greg Iles Feb Optical Global Trigger Interface Card Dual CMC card with Virtex 5 LX110T 16 bidirectional.

Mini scope one semester project Project final Presentation Svetlana Gnatyshchak Lior Haiby Advisor: Moshe Porian Febuary 2014.

11 th April 2003L1 DCT Upgrade FDR – TSF SessionMarc Kelly University Of Bristol On behalf of the TSF team Firmware and Testing on the TSF Upgrade Marc.

Lab Environment and Miniproject Assignment Spring 2009 ECE554 Digital Engineering Laboratory.

XTRP Software Nathan Eddy University of Illinois 2/24/00.

Level-1 Trigger Commissioning Status A.Somov Jefferson Lab Collaboration Meeting, May 10, 2010.

Internal Logic Analyzer Characterization presentation By: Moran Katz and Zvika Pery Mentor: Moshe Porian Dual-semester project Spring 2012.

CPT week May 2003Dominique Gigi CMS DAQ 1.Block diagram 2.Form Factor 3.Mezzanine card (transmitter SLINK64) 4.Test environment 5.Test done 1.Acquisition.

SL-PGA firmware overview M. Sozzi Pisa - January 30/31, 2014.

General Tracker Meeting: Greg Iles4 December Status of the APV Emulator (APVE) First what whyhow –Reminder of what the APVE is, why we need it and.

29 May 2009 Henk Boterenbrood, Augusto Ceccucci, Bjorn Hallgren, Mauro Piccini and Helmut Wendler 1 The Calorimeter Recorder CARE.

Rutherford Appleton Laboratory September 1999Fifth Workshop on Electronics for LHC Presented by S. Quinton.

INSIDE – Update meeting PET DAQ 24 March Refresh from the last meetings Objectives of the PET DAQ – Provide a full in-beam (full-beam) PET system.

WINLAB Open Cognitive Radio Platform Architecture v1.0 WINLAB – Rutgers University Date : July 27th 2009 Authors : Prasanthi Maddala,

March 27, 2013KM3NeT, CLBv2 Meeting Peter Jansweijer Mesfin Gebyehu Nikhef Amsterdam Electronics- Technology KM3NeT CLBv2 1.

Integration with ATLAS DAQ Marcin Byszewski 23/11/2011 RD51 Mini week Marcin Byszewski, CERN1.

Electronic System Design GroupInstrumentation DepartmentR. Halsall, S. Taghavirad et alRutherford Appleton Laboratory5 March 2003 CMS Tracker FED Firmware.

Status report 2011/7/28 Atsushi Nukariya. Progress Progresses are as follows. 1. FPGA -> Analyze data from FPGA, and some revise point is found. 2. Software.

Status report 2011/7/15 Atsushi Nukariya. Progress Progresses are as follows. 1. GEMFE2 Chip -> The signal is seen. 2. FPGA -> Data format is changed.

Status and Plans for Xilinx Development

Trigger Gigabit Serial Data Transfer Walter Miller Professor David Doughty CNU October 4, 2007.

Calliope-Louisa Sotiropoulou FTK: E RROR D ETECTION AND M ONITORING Aristotle University of Thessaloniki FTK WORKSHOP, ALEXANDROUPOLI: 10/03/2014.

ATLAS Pre-Production ROD Status SCT Version

Status of NA62 straw readout

Initial check-out of Pulsar prototypes

Enrico Gamberini for the GTK WG TDAQ WG Meeting June 01, 2016

Meeting at CERN March 2011.

MULTIBOOT AND SPI FLASH MEMORY

8-layer PC Board, 2 Ball-Grid Array FPGA’s, 718 Components/Board

The CMS Tracking Readout and Front End Driver Testing

TELL1 A common data acquisition board for LHCb

Presentation transcript:

GCT Meeting: DTPM Status: Greg Iles1 July DTPM Fundamentals TPMs 0 to 7 send event data and status and receive control Receive TPM event data Buffer event data, insert checksums and control readout CM receives event data and status and sends control Verify data and send to CM Receive control and forward to fpga c0 for distribution (indirect) FPGAs : i2/i3FPGAs : p3FPGAs : ro, r1 and r3 Send status info to CM Merge status information and record history Receive TPM status data Event dataControlStatus

GCT Meeting: DTPM Status: Greg Iles1 July DTPM Status Rx Data SimTPM Tx Cntrl Verify TPM0 Input (rx) TPM1 Input (rx) TPM7 Input (rx) TPM Buf (p3) TPM0 Data Data DPM Data size FIFO Check & pad Verify TPM1 Data TPM7 Data Mux Data Merge Status from DPM and FIFO buffer levels Event header Chksum (p3) Insert Link0, Ch0 Chksum (i2) Verify Ch0 Verify Ch1 Ser (i2) Tx Evnt Tx Status Tx Evnt Rx Cntrl Chksum (i2)Ser (i3) Insert Link0, Ch1 Insert Link0, Ch1 Insert Link1, Ch1 TPMs 0 to 7 send event data and receive cntrl Conn (xx)ControlBus (c0) WB Comm Readout Sync Cntrl Status FPGA Bypass Duplicate for TPMs 2-6 Duplicate for TPMs 2-6 history Status (all) merge Cntrl (all) respond to cntrl CM receives event data and sends cntrl Bristol : DoneCERN : DoneBristol : PendingCERN: Pending

GCT Meeting: DTPM Status: Greg Iles1 July Progress Progress –20/6: Programmed DTPM FPGAs r0, p3 and i2 via compact flash Would have allowed fake TPM data generated in r0 to be propagated through p3 and into i2. Able to communicate with p3 Unable to communicate with r0 or i2 or any other chip on control bus A. Works OK in simulation. Rather than debug we wait for new control bus. –23/6: Synthesized i3. Sufficient FPGA code to now link to CM –28/6: Simulation of virtual CM-DTPM SerDes links Works well in simulation. –29/6: First iteration of history block (maybe used by TPMs & CM) Needs some additional features

GCT Meeting: DTPM Status: Greg Iles1 July Plan Data –Add verification check to incoming data from TPMs. Links to and from CM and event blocks generated in p3 are protected with error checking.Control –Need to make sure that all units respond in a sensible fashion to TTC control signals (e.g. state machine ought to come out of error on resync).Status –Provide method for storing and merging status (e.g. READY, BUSY, etc) and their origins (e.g. what caused the board to flip into BUSY) Software & Testing –As soon as the new control bus is finished we can start testing. Ideally want the final software access to wishbone slaves in place soon. PS Probably shouldn’t mentions thing like this, however: I thought there was a rough plan to have finished DTPM-CM integration by end of June and TPM-DTPM-CM integration by end of July. Any thoughts......