Overview Why VLSI? Moore’s Law. The VLSI design process.

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Presentation transcript:

Overview Why VLSI? Moore’s Law. The VLSI design process. IP-based design.

Why VLSI? Integration improves the design: lower parasitics = higher speed; lower power; physically smaller. Integration reduces manufacturing cost-(almost) no manual assembly.

VLSI and you Microprocessors: DRAM/SRAM. Special-purpose processors. personal computers; microcontrollers. DRAM/SRAM. Special-purpose processors.

Moore’s Law Gordon Moore: co-founder of Intel. Predicted that number of transistors per chip would grow exponentially (double every 18 months). Exponential improvement in technology is a natural trend: steam engines, dynamos, automobiles.

Moore’s Law plot

Moore’s Law and Intel processors

Moore/Intel log scale

Terminology Manufacturing node: technology at a particular channel length. Deep submicron technology: 250-100 nm. Nanometer technology: 100 nm and below.

The cost of fabrication Current cost: $4 billion. Typical fab line occupies about 1 city block, employs a few hundred people. Most profitable period is first 18 months-2 years.

Cost factors in ICs For large-volume ICs: packaging is largest cost; testing is second-largest cost. For low-volume ICs, design costs may swamp all manufacturing costs.

Cost of design Design cost can be significant: $20 million for a large ASIC, $500 million for a large CPU. Cost elements: Architects, logic designers, etc. CAD tools. Computers the CAD tools run on.

Intellectual property Intellectual property (IP): pre-designed components. May come from outside vendors, internal sources. IP saves time, design cost. IP blocks must be designed to be reused.

Reliability Nanometer technologies require attention to reliability. Design-for-manufacturing (DFM) and design-for-yield (DFY) techniques adjust the design to improve yield. Circuit and architecture techniques can compensate for unreliable components.

The VLSI design process May be part of larger product design. Major levels of abstraction: specification; architecture; logic design; circuit design; layout.

Challenges in VLSI design Multiple levels of abstraction: transistors to CPUs. Multiple and conflicting constraints: low cost and high performance are often at odds. Short design time: Late products are often irrelevant.

Dealing with complexity Divide-and-conquer: limit the number of components you deal with at any one time. Group several components into larger components: transistors form gates; gates form functional units; functional units form processing elements; etc.

Hierarchical name Interior view of a component: components and wires that make it up. Exterior view of a component = type: body; pins. cout Full adder sum a b cin

Instantiating component types Each instance has its own name: add1 (type full adder) add2 (type full adder). Each instance is a separate copy of the type: cout Add1.a Add2.a Add2(Full adder) Add1(Full adder) sum sum a a b b cin cin

A hierarchical logic design box1 box2 x z

Net lists and component lists net1: top.in1 in1.in net2: i1.out xxx.B topin1: top.n1 xxx.xin1 topin2: top.n2 xxx.xin2 botin1: top.n3 xxx.xin3 net3: xxx.out i2.in outnet: i2.out top.out Component list: top: in1=net1 n1=topin1 n2=topin2 n3=topine out=outnet i1: in=net1 out=net2 xxx: xin1=topin1 xin2=topin2 xin3=botin1 B=net2 out=net3 i2: in=net3 out=outnet

Component hierarchy top i1 xxx i2

Hierarchical names Typical hierarchical name: top/i1.foo component pin

Layout and its abstractions Layout for dynamic latch:

Stick diagram

Transistor schematic

Mixed schematic inverter

Levels of abstraction Specification: function, cost, etc. Architecture: large blocks. Logic: gates + registers. Circuits: transistor sizes for speed, power. Layout: determines parasitics.

Circuit abstraction Continuous voltages and time:

Digital abstraction Discrete levels, discrete time:

Register-transfer abstraction Abstract components, abstract data types: 0010 + 0001 + 0011 0100

Top-down vs. bottom-up design Top-down design adds functional detail. Create lower levels of abstraction from upper levels. Bottom-up design creates abstractions from low-level behavior. Good design needs both top-down and bottom-up efforts.

Design abstractions specification behavior function cost logic circuit English Executable program Sequential machines Logic gates transistors rectangles specification Throughput, design time Function units, clock cycles Literals, logic depth nanoseconds microns behavior function cost register- transfer logic circuit layout

Design validation Must check at every step that errors haven’t been introduced-the longer an error remains, the more expensive it becomes to remove it. Forward checking: compare results of less- and more-abstract stages. Back annotation: copy performance numbers to earlier stages.

Manufacturing test Not the same as design validation: just because the design is right doesn’t mean that every chip coming off the line will be right. Must quickly check whether manufacturing defects destroy function of chip. Must also speed-grade.

IP-based design Almost every chip uses some form of IP: Standard cell libraries. Memories. IP blocks. Designers must know how to: Create IP. Use IP.

Types of IP Hard IP: Soft IP: Pre-designed layout. Allows more detailed characterization. Soft IP: No layout---logic synthesis, etc. IP layout is created by the IP user.

Hard IP Must conform to many standards: Layout pin placement. Layer usage. Transistor sizing. Hard IP blocks are usually qualified on a particular process. Component is fabricated and tested to show that the IP works on that fab line.

Soft IP Conformance of layout to local standards is easier since it is created by the user. Timing can only be estimated until the layout is done. Must conform to interface standards. A wrapper adapts a block to a new interface.

IP across the design hierarchy Standard cells. Pitch matched in rows, compatible drive. Register-transfer modules. Memories. CPUs. Busses. I/O devices.

Specifying IP Hard or soft? Functionality. Performance, including process corners. Power consumption. Special process features required.

The I/O lifecycle spec HDL design extraction validation documentation IP docs IP database qualification IP modules chip design

Using IP May come from vendor, open source, or internal group. Must identify candidate IP, evaluate for suitability. May have to pay for IP. May want to qualify IP before use, particularly if it pushes analog characteristics.