Advertisement In this work we presents novel and efficient methods for on- line CLB testing in FPGA’s. We use a ROving Tester (ROTE) which unlike any prior.

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Presentation transcript:

Advertisement In this work we presents novel and efficient methods for on- line CLB testing in FPGA’s. We use a ROving Tester (ROTE) which unlike any prior work has has provable diagnosability. The ROTE consists of multiple Built-In-Self-Testers (BISTers). We present 1- and 2- diagnosable BISTer designs. We also introduce a functionality-based testing technique, Fast-Test-and-Diagnosis (Fast-TAD) which tests each CLB in only two configurations compared to exhaustive CLB testing of previous work. All these techniques combined lead to more accurate and faster test and diagnosis of FPGAs than any previous method.

Roving Tester (ROTE) with Built-in-Self-Testers (BISTers) ROTE Circuit Spare column ROTE Spare column BISTer Roving Testing Using New Built-in- Self-Tester Designs for FPGA’s Vinay Verma (Xilinx Inc. ) Shantanu Dutt (Univ.of Illinois at Chicago)

Salient Features of our Methodology Two columns of FPGA left spare for the ROTE; and 1 column as spare for the fault reconfiguration. Fault detections consists of output response of two identically configured CLB’s. A mismatch indicates fault in BISTer tile. Bister designs with provable diagnosabilities, not adaptive as in some prior works. Methodology for fast and 1-diagnosable functional testing.

Our BISTer-1 Architecture Cycling of CLBs in BISTer C TPG BUT ORA A B D BUT: Block(CLB) Under Test ORA: Output Response Analyser TPG: Test Pattern Generator A B C D TPG ORA BUT ORABUT S1S2S3S4 Sess  CLB  TPGBUT ORA B A CD

Gross PASS-FAIL Syndromes of BISTer-1 CLB A is configured as BUT is S3, S4 and as TPG in S1. When faulty CLB is TPG then the output is PASS and whenever it is a BUT, the output is FAIL. Theorem 1:BISTer-1 is 1-diagnosable, i.e., it can detect and locate one faulty CLB among its four CLB’s.

BISTer-2 D ORA C BUTTPG BUTTPG ORA A B E F Y2Y1 One full BISTer cycle through 6 session Its 6 CLB architecture. 2 CLB’s as TPG and 2 CLB’s as ORA. First ORA(Y1) compares outputs of 2-BUTs and second ORA(Y2) compares outputs of 2-TPG’s

BISTEer-2 Gross Pass/Fail syndromes at both ORA’s Theorem 2: BISTer-2 is 2-diagnosable with very high probability

Fast-TAD: Fast Functional Testing and Diagnosis In this methodology a CLB is tested only for specific configurations/functions it will assume as the ROTE moves across the FPGA. A CLB X is functionally-faulty (f-faulty) if faults in X produce incorrect outputs, when X implements any of its operational functions. Property: While roving the ROTE in an FPGA either without f-faults or with reconfigured f-faults, a CLB needs to implement at most two functions: its original function (when ROTE is in its initial position) and the function of the CLB two f-fault-free CLBs in the same row in the direction of ROTE movement.

CLB-functionality with ROTE movement CLB in column c3 implements function fx1 in (a) and function fx3 in (d) as the ROTE moves across the FPGA. c1 c2 c3 c4 c5 fx1fx2fx3 ROTE (a) c1 c2 c3 c4 c5 fx1fx2fx3 ROTE (b) c1 c2 c3 c4 c5 fx1fx2fx3 ROTE (c) c1 c2 c3 c4 c5 fx1fx2fx3 ROTE (d)

Diagnosis in Fast-TAD Theorem 3: Fast-TAD using Bister-1 can diagnose 1 f-faulty PLB in each Bister-1 tile of 2x2 CLBs. Each CLB is tested with 2 sets of configurations only. When the f-faulty CLB is configured as a TPG, the gross syndrome is pass and when it is configured as a BUT and implements its operational functions, then the gross syndrome is fail. In all other cases it is either a pass or a fail. The second test set is used to distinguish between the possible f-fault being in either of A,C or in either of B,D.