Final Project Overall Design Presented By: Akram Ahmed Date: 19 November 2014 CMPE 691: Digital Signal Processing Hardware Implementation

Outline  Filter Design  Window Design  Complex Number  Absolute Value Calculation  City Distance  Spectral Density Design  FFT Latency and selection  Overall Design

Filter Design  Number of Taps: 201  Max Filter Coeff =  Min Filter Coeff Value =  Coeff representation = 1.9, signed 2’s compliment

Window Design  Max Window Coeff = 1  Min Window Coeff Value = (non-zero)  Coeff representation = 1. 9, unsigned

Combined Filter and Window

Spectral Density

FFT  Number of Inputs: 1024  Target Design Frequency: 50 MHz (20ns)  FFT Latency = FFT calculation time + drain time  For Radix 2 lite  FFT Latency =  s * 20 ns = ms  For Radix 2 Burst I/O  FFT Latency =  s * 20 ns = ms  For Radix 4 Burst I/O  FFT Latency =  s * 20 ns = ms  For Pipeline Streaming  FFT Latency =  s * 20 ns = ms

Overall Design

FIR IP Core

FIR Simulation

FIR Matlab f = fopen ('filtInp','w'); filtLen = length(y1); for i = 1:1:filtLen nonF = fi(y1(i),1,16,0); fprintf(f,'%s,\n', nonF.bin); fix = strcat(nonF.bin,'.0'); y1(i) = fix2dec(fix); end

FIR Simulated output and Matlab comp.

FIR input

Overall Design