CIS 540 Principles of Embedded Computation Spring 2015 Instructor: Rajeev Alur

Slides:



Advertisements
Similar presentations
Great Theoretical Ideas in Computer Science for Some.
Advertisements

Partial Order Reduction: Main Idea
CIS 540 Principles of Embedded Computation Spring Instructor: Rajeev Alur
Decomposing Refinement Proofs using Assume-Guarantee Reasoning Tom Henzinger (UC Berkeley) Shaz Qadeer (Compaq Research) Sriram Rajamani (Microsoft Research)
CIS 540 Principles of Embedded Computation Spring Instructor: Rajeev Alur
Supervisory Control of Hybrid Systems Written by X. D. Koutsoukos et al. Presented by Wu, Jian 04/16/2002.
CIS 540 Principles of Embedded Computation Spring Instructor: Rajeev Alur
CompSci 102 Discrete Math for Computer Science April 19, 2012 Prof. Rodger Lecture adapted from Bruce Maggs/Lecture developed at Carnegie Mellon, primarily.
Discrete Mathematics Lecture 5 Alexander Bukharovich New York University.
Interface-based design Philippe Giabbanelli CMPT 894 – Spring 2008.
Parallel Scheduling of Complex DAGs under Uncertainty Grzegorz Malewicz.
CIS 540 Principles of Embedded Computation Spring Instructor: Rajeev Alur
CIS 540 Principles of Embedded Computation Spring Instructor: Rajeev Alur
EECS 20 Lecture 38 (April 27, 2001) Tom Henzinger Review.
Transaction Processing Lecture ACID 2 phase commit.
ECE 331 – Digital System Design
CSE 421 Algorithms Richard Anderson Lecture 4. What does it mean for an algorithm to be efficient?
Expressing Giotto in xGiotto and related schedulability problems Class Project Presentation Concurrent Models of Computation for Embedded Software University.
Creating Packages. 2 home back first prev next last What Will I Learn? Describe the reasons for using a package Describe the two components of a package:
November 18, 2004 Embedded System Design Flow Arkadeb Ghosal Alessandro Pinto Daniele Gasperini Alberto Sangiovanni-Vincentelli
Mahapatra-A&M-Sprong'021 Co-design Finite State Machines Many slides of this lecture are borrowed from Margarida Jacome.
EECS 20 Chapter 3 Sections State Machines Continued Last time we Introduced the deterministic finite state machine Discussed the concept of state.
SE-565 Software System Requirements More UML Diagrams.
Ch.2 Part A: Requirements, State Charts EECE **** Embedded System Design.
CIS 540 Principles of Embedded Computation Spring Instructor: Rajeev Alur
Instruction Sets and Pipelining Cover basics of instruction set types and fundamental ideas of pipelining Later in the course we will go into more depth.
CIS 540 Principles of Embedded Computation Spring Instructor: Rajeev Alur
Instructor: Rajeev Alur
Copyright 2002 Prentice-Hall, Inc. Modern Systems Analysis and Design Third Edition Jeffrey A. Hoffer Joey F. George Joseph S. Valacich Chapter 20 Object-Oriented.
CIS 540 Principles of Embedded Computation Spring Instructor: Rajeev Alur
1 2. Independence and Bernoulli Trials Independence: Events A and B are independent if It is easy to show that A, B independent implies are all independent.
Foundations of Software Testing Chapter 1: Preliminaries Last update: September 3, 2007 These slides are copyrighted. They are for use with the Foundations.
CIS 540 Principles of Embedded Computation Spring Instructor: Rajeev Alur
CIS 842: Specification and Verification of Reactive Systems Lecture Specifications: LTL Model Checking Copyright , Matt Dwyer, John Hatcliff,
Ch. 2. Specification and Modeling 2.1 Requirements Describe requirements and approaches for specifying and modeling embedded systems. Specification for.
CIS 540 Principles of Embedded Computation Spring Instructor: Rajeev Alur
CIS 540 Principles of Embedded Computation Spring Instructor: Rajeev Alur
HAWKES LEARNING SYSTEMS math courseware specialists Copyright © 2011 Hawkes Learning Systems. All rights reserved. Hawkes Learning Systems: College Algebra.
Relations and their Properties
CIS 540 Principles of Embedded Computation Spring Instructor: Rajeev Alur
CIS 540 Principles of Embedded Computation Spring Instructor: Rajeev Alur
Mathematical Preliminaries
School of Computer Science, The University of Adelaide© The University of Adelaide, Control Data Flow Graphs An experiment using Design/CPN Sue Tyerman.
CIS 540 Principles of Embedded Computation Spring Instructor: Rajeev Alur
CIS 540 Principles of Embedded Computation Spring Instructor: Rajeev Alur
SECTION 9 Orbits, Cycles, and the Alternating Groups Given a set A, a relation in A is defined by : For a, b  A, let a  b if and only if b =  n (a)
High Performance Embedded Computing © 2007 Elsevier Chapter 1, part 3: Embedded Computing High Performance Embedded Computing Wayne Wolf.
CIS 540 Principles of Embedded Computation Spring Instructor: Rajeev Alur
CIS 540 Principles of Embedded Computation Spring Instructor: Rajeev Alur
CompSci 102 Discrete Math for Computer Science March 13, 2012 Prof. Rodger Slides modified from Rosen.
CMPSC 16 Problem Solving with Computers I Spring 2014 Instructor: Tevfik Bultan Lecture 4: Introduction to C: Control Flow.
ECE 448 Lecture 6 Finite State Machines State Diagrams vs. Algorithmic State Machine (ASM) Charts.
High Performance Embedded Computing © 2007 Elsevier Lecture 4: Models of Computation Embedded Computing Systems Mikko Lipasti, adapted from M. Schulte.
CIS 540 Principles of Embedded Computation Spring Instructor: Rajeev Alur
CIS 540 Principles of Embedded Computation Spring Instructor: Rajeev Alur
Chromatic Coloring with a Maximum Color Class Bor-Liang Chen Kuo-Ching Huang Chih-Hung Yen* 30 July, 2009.
CIS 540 Principles of Embedded Computation Spring Instructor: Rajeev Alur
CIS 540 Principles of Embedded Computation Spring Instructor: Rajeev Alur
CIS 540 Principles of Embedded Computation Spring Instructor: Rajeev Alur
CIS 540 Principles of Embedded Computation Spring Instructor: Rajeev Alur
CPE555A: Real-Time Embedded Systems
Graph Coverage for Specifications CS 4501 / 6501 Software Testing
Instructor: Rajeev Alur
ECE 448 Lecture 6 Finite State Machines State Diagrams vs. Algorithmic State Machine (ASM) Charts.
CHAPTER 4 Test Design Techniques
Autonomous Cyber-Physical Systems: Synchronous Components: II
Chapter 20 Object-Oriented Analysis and Design
Spring CS 599. Instructor: Jyo Deshmukh
Instructor: Aaron Roth
Instructor: Aaron Roth
Presentation transcript:

CIS 540 Principles of Embedded Computation Spring Instructor: Rajeev Alur

Example Task Graph in1 out1 A1: x1,in1 -> y,x1 in2 out2 out3 x1, x2 local y A2: x2 -> out2 A3: x1,in1 -> out1,x1 A4: in2,y,out2 -> x2,out3  What are possible schedules consistent with precedence constraints?  What are I/O await dependencies? CIS 540 Spring 2015; Lecture Jan 28

Task Graphs: Definition  For a synchronous reactive component C with input vars I, output vars O, state vars S, and local vars L, reaction description is given by a set of tasks, and precedence edges < over these tasks  Each task A is specified by: 1.Read-set R  must be a subset of I U S U O U L 2.Write-set W  must be a subset of O U S U L 3.Update: code to write vars in W based on values of vars in R  [Update] is a subset of Q R x Q W CIS 540 Spring 2015; Lecture Jan 28

Requirements on Task Graph (1) The precedence relation < must be acyclic  Notation: A’ < + A means that there is a path from task A’ to task A in the task graph using precedence edges  < + denotes the “transitive closure” of the relation <  Task schedule: Total ordering A 1, A 2,.. A n of all the tasks consistent with the precedence edges  If A’ < A, then A’ must appear before A in the ordering  Multiple schedules possible  If A’ < + A then A’ must appear before A in every schedule  Acyclicity means that there is at least one task schedule CIS 540 Spring 2015; Lecture Jan 28

Requirements on Task Graph (2) Each output variable is in the write-set of exactly one task  If output y is in write-set of task A, then as soon as A executes the output y is available to the rest of the system  If task A writes output y, then y awaits an input variable x, denoted y > x, if either the task A reads x or another task A’ reads x such that A’ < + A  y awaits x means that y cannot be produced before x is supplied CIS 540 Spring 2015; Lecture Jan 28

Requirements on Task Graph (3) Output/local variables are written before being read:  If an output or a local variable y is in the read-set of a task A, then y must be in the write-set of some task A’ such that A’ < + A CIS 540 Spring 2015; Lecture Jan 28

Requirements on Task Graph (4)  Write-conflict between tasks A and A’:  There exists a variable that A writes and is either read or written by A’  If A and A’ have write-conflict, then the result depends on whether A executes before A’ or vice versa.  Example: Update of A is x := x+1; Update of A’ is out := x  Requirement: Tasks with a write conflict must be ordered:  If tasks A and A’ have write-conflict then either A < + A’ or A’ < + A  The set of reactions resulting from executing all the tasks do not depend on the task schedule CIS 540 Spring 2015; Lecture Jan 28

Properties of Tasks  Task A = (R, W, Update) is deterministic if for every value u in Q R there is a unique value v in Q W such that (u,v) is in [Update]  If all tasks of a component are deterministic, what can we conclude about the component itself?  Task A = (R, W, Update) is input-enabled if for every value u in Q R there exists at least one value v in Q W such that (u,v) is in [Update]  If all tasks of a component are input-enabled, what can we conclude about the component itself? CIS 540 Spring 2015; Lecture Jan 28

Interfaces bool in bool x := 0 out:=x ; x:= in bool out Delay  Interface = Input variables, Output variables, Await dependencies bool in bool x := 0 out:=x ; x:= in bool out Delay A: x,in -> out,x bool inbool out awaits in Delay Interface CIS 540 Spring 2015; Lecture Jan 28

Interface: SplitDelay bool inbool out SplitDelay Interface bool in bool x := 0 out:=x bool out SplitDelay A1: x -> out A2: in -> x x:=in CIS 540 Spring 2015; Lecture Jan 28

Example Interface in1 out1 A1: x1,in1 -> y,x1 in2 out2 out3 x1, x2 local y A2: x2 -> out2 A3: x1,in1 -> out1,x1 A4: in2,y,out2 -> x2,out3 awaits in1 awaits in1, in2 CIS 540 Spring 2015; Lecture Jan 28

Back to Parallel Composition  Relay and Inverter are not compatible since there is a cycle in their combined await dependencies Relay Inverter bool out awaits in bool in awaits out CIS 540 Spring 2015; Lecture Jan 28

Composing SplitDelay and Inverter  SplitDelay and Inverter are compatible since there is no cycle in their combined await dependencies  Note: Delay and Inverter are not compatible SplitDelay Inverter bool out bool in awaits out CIS 540 Spring 2015; Lecture Jan 28

Component Compatibility Definition  Given:  Component C1 with input vars I1, output vars O1, and awaits- dependency relation > 1  Component C2 with input vars I2, output vars O2, and awaits- dependency relation > 2  The components C1 and C2 are compatible if  No common outputs: sets O1 and O2 are disjoint  The relation (> 1 U > 2 ) of combined await-dependencies is acyclic  Parallel Composition is allowed only for compatible components CIS 540 Spring 2015; Lecture Jan 28

Defining the Product bool in bool temp Delay1 bool out Delay2 bool x1 := 0 temp:=x1 ; x1:= in bool x2 := 0 out:=x2 ; x2:= temp Delay1 || Delay2 bool in bool out bool temp bool x1 := 0; x2:=0 temp:=x1 ; x1:= in A1 : in, x1 -> temp, x1 out:=x2 ; x2:= temp A2 : temp, x2 -> out, x2 A1 : in, x1 -> temp, x1 A2 : temp, x2 -> out, x2 CIS 540 Spring 2015; Lecture Jan 28

Composing SplitDelay and Inverter bool in bool x := 0 out:=x bool out SplitDelay A1: x -> out A2: in -> x x:=in A: out -> in in := ~ out Inverter SplitDelay || Inverter bool out bool in bool x := 0 out := x A1 : x -> out x := in A2 : in -> x A: out -> in in := ~ out CIS 540 Spring 2015; Lecture Jan 28

Parallel Composition Definition  Given compatible components C1 = (I1,O1,S1,Init1,React1) and C2 = (I2,O2,S2, Init2,React2), what’s the definition of product C = C1 || C2?  We already defined I, O, S, and Init for C  Suppose React1 specified using local variables L1, set of tasks  1, and precedence < 1, and React2 given using local vars L2, set of tasks  2, and precedence < 2  Reaction description for product C has  Local variables L1 U L2  Set of tasks  1 U  2  Precedence edges: Edges in < 1 + Edges in < 2 + Edge between tasks A1 and A2 of different components if A2 reads a var written by A1 CIS 540 Spring 2015; Lecture Jan 28

Parallel Composition Definition  Why is the parallel composition operation well-defined?  Can the new edges make task graph of the product cyclic?  Recall: Await-dependencies among I/O variables of compatible components must be acyclic  Proposition 2.1: Awaits compatibility implies acyclicity of product task graph  Bottomline: Interfaces capture enough information to define parallel composition in a consistent manner  Aside: possible to define more flexible (but complex) notions of awaits dependencies CIS 540 Spring 2015; Lecture Jan 28

Properties of Parallel Composition  Commutative: C1 || C2 is same as C2 || C1  Associative: Given C1, C2, C3, all of (C1||C2)||C3, C1||(C2||C3), (C1||C3)||C2, … give the same result  If compatibility check fails in one case, will also fail in others  Bottomline: Order in which components are composed does not matter  If both C1 and C2 are finite-state, then so is product C1||C2  If C1 has n1 states and C2 has n2 states then the product has (n1 x n2) states  If both C1 and C2 are deterministic, then so is product C1||C2  If both C1 and C2 are event-triggered, is it guaranteed that the product C1||C2 is event-triggered?? CIS 540 Spring 2015; Lecture Jan 28

Output Hiding  Given a component C, and an output variable y, the result of hiding y in C, written as C\y, is basically the same component as C, but y is no longer an output variable, and becomes a local variable  Not available to the outside world  Useful for limiting the scope (encapsulation) CIS 540 Spring 2015; Lecture Jan 28

DoubleDelay bool in bool temp Delay1 bool out Delay2 bool x1 := 0 temp:=x1 ; x1:= in bool x2 := 0 out:=x2 ; x2:= temp (Delay1 || Delay2) \ temp bool in bool out bool x1 := 0; x2:=0 temp:=x1 ; x1:= in A1 : in, x1 -> temp, x1 out:=x2 ; x2:= temp A2 : temp, x2 -> out, x2 A1 : in, x1 -> temp, x1 A2 : temp, x2 -> out, x2 local bool temp CIS 540 Spring 2015; Lecture Jan 28

Second-To-Minute event second int x := 0 if second? then { x:=x+1; if x==60 then { minute!; x :=0 } } event minute Desired behavior (spec): Issue the output event every 60 th time the input event is present  Design the component Second-To-Hour such that it issues its output every 3600 th time its input event is present CIS 540 Spring 2015; Lecture Jan 28 SecondToMinute

Synchronous Block Diagrams CIS 540 Spring 2015; Lecture Jan 28

Homework 1  Five problems (25pts total) 1.Exercise Exercise Exercise Exercise Exercise 2.23  Due on Wed, Feb 4, in class  Note: We will cover Section 2.4 in class on Monday  Recitation on Friday  Lecture slides posted at CIS 540 Spring 2015; Lecture Jan 28