Outline Memory characteristics SRAM Content-addressable memory details DRAM © Derek Chiou & Mattan Erez 1

2 What Memory Should I Use? Depends on access characteristics How often is it written? How often is it accessed in general? How fast should the accesses be? Latency? Bandwidth? What should the capacity be? Bytes? Kilobytes? Megabytes? Gigabytes? Terbytes? How long should the data last? Microseconds? Seconds? Years? Decades? Different memories optimized for different access types SRAM, DRAM, FLASH, STT-RAM, Phase Change, magnetic disk…

© Derek Chiou & Mattan Erez 3 What Memory Should I Use? Depends on access characteristics How often is it written? How often is it accessed in general? How fast should the accesses be? Latency? Bandwidth? What should the capacity be? Bytes? Kilobytes? Megabytes? Gigabytes? Terbytes? How long should the data last? Microseconds? Seconds? Years? Decades? Granularity of access Cost Dollars, watts or joules, … Different memories optimized for different access types

© Derek Chiou & Mattan Erez 4 Memory Types ROM (non-volatile Read Only Memory) RAM (volatile, Random Access Memory) “Disk” Non-mainstream Really misnomers today RAM is often not truly random access ROM is writable, just more slowly than RAM

© Derek Chiou & Mattan Erez 5 Read-Only Memory (ROM) Why? ROM Manufacture time Programmable ROM (PROM) Program once EPROM (Erasable PROM) Program many times Use UV light to erase EEPROM (Electrically Erasable PROM) Program many times Convenient FLASH (not a ROM, but used in ROM applications) Program many times Fairly fast (~100ns) Wear out

© Derek Chiou & Mattan Erez 6 Random Access Memory (RAM) Static RAM (SRAM) “Static” indicates that as long as you apply power, the value will be maintained 6 transistors/bit Dynamic RAM (DRAM) What does dynamic mean? Capacitor stores data (1 cap + 1 transistor/bit) Interfaces DDR – double data rate Burst mode – most DRAMs have a burst of at least 4 (now 8)

SRAM © Derek Chiou & Mattan Erez 7

8 SRAM Cell (6T) word line =

© Derek Chiou & Mattan Erez 9 SRAM Array word line 0 word line 1 b0 b1 b2 b3 word line 2 word line 3

© Derek Chiou & Mattan Erez 10 Accessing SRAM Can read/write (modulo bus turnaround) every cycle Generally 1 cycle latency (could be longer based on pipelining) Large SRAMs are slower than smaller SRAMs

CAM © Derek Chiou & Mattan Erez 11

© Derek Chiou & Mattan Erez 12 Implementing a CAM Implement it with SRAMs (directly addressable memory) Program some sort of content search Takes time and resources Really, just an algorithm on top of directly addressable memory Implement with special circuits

© Derek Chiou & Mattan Erez 13 Implementing a CAM Implement with special circuits

© Derek Chiou & Mattan Erez 14 Implementing a CAM Implement with special circuits

DRAM © Derek Chiou & Mattan Erez 15

© Derek Chiou & Mattan Erez 16 DRAM Cell What happens when you read? 16

© Derek Chiou & Mattan Erez 17 DRAM Cell What happens when you read? Infineon 80nm 17

© Derek Chiou & Mattan Erez 18 DRAM Refresh Capacitor holding value leaks, eventually you will lose information (everything turns to 0) How do you maintain the values in DRAM? 18

© Derek Chiou & Mattan Erez 19 Simplified DRAM Internal Structure Row Column RAS CAS Addr 19

© Derek Chiou & Mattan Erez 20 Simplified DRAM Internal Structure Row Column RAS CAS Addr 20

© Derek Chiou & Mattan Erez 21 DRAM Sense Amplifier

© Derek Chiou & Mattan Erez 22 DRAM Array

© Derek Chiou & Mattan Erez 23 Accessing DRAM (RAS) Operation Resource Utilization Cycle Activate Row Request Data request data Simplified Bank State Diagram act prewr rd Row decoder Sense amplifier Column decoder DRAM Memory array bank 0

© Derek Chiou & Mattan Erez 24 Accessing DRAM (CAS) Operation Resource Utilization Row decoder Sense amplifier Column decoder DRAM Memory array bank 0 request data Simplified Bank State Diagram act prewr rd Read Row Request Data Cycle

© Derek Chiou & Mattan Erez 25 Accessing DRAM (re-writing “lost” data) Operation Resource Utilization Precharge Row Request Data request data Simplified Bank State Diagram act pre wr rd Row decoder Sense amplifier Column decoder DRAM Memory array bank 0 Cycle

© Derek Chiou & Mattan Erez 26 DRAM RAS/CAS Summary Assert RAS to specify row address Assert CAS to specify column address Why separate RAS/CAS? Can pulse CAS to read more from the same row Faster Implications? Called Fast Page Mode 26

What to do while waiting for Act/Pre/…? © Derek Chiou & Mattan Erez 27 request data bank n-1bank 1 Row decoder Sense amplifier Column decoder DRAM Memory array bank 0

© Derek Chiou & Mattan Erez 28 DRAM Hierarchy/Banks Row Column RAS CAS Bank[1:0] Why have banks? Cannot access banks back-to-back. Why?

© Derek Chiou & Mattan Erez 29 Memory Interfaces How much data per column command? Interface width (x4, x8, …) How much data per bus transfer Note: each column DRAM address refers to width bits Burst length (4, 8, …) How many bus transfers per CAS SDRAM Synchronous DRAM – more when we discuss buses DDRx Double-data rate – multiple data transfers per clock (rising and falling edge, or even faster) DDR, then DDR2, then DDR3 – just different standards for defining sizing, timing, and electrical parameters

© Derek Chiou & Mattan Erez 30 Tradeoffs: SRAM vs DRAM CriteriaSRAMDRAM SpeedLow LatencyHigh Bandwidth StaticYesNo AccessEasyHarder ProcessLogicDRAM RefreshNoYes DensityLowHigh 30

© Derek Chiou & Mattan Erez 31 Real RAM Configurations DDR3 SDRAM (Micron’s latest) This year 4Gb (sampling max speed is 667MHz, 1333Mb data speeds) 2Gb (max speed is 667MHz, 1333Mb data speeds) 1Gb (max speed is 800MHz, 1600Mb data speeds) Last year 4Gb (max speed is 533MHz, 1066Mb data speeds), TwinDie  64M x 4 x 8 banks x 2 ranks  32M x 8 x 8 banks x 2 ranks 2Gb (max speed is 667MHz, 13333Mb data speeds) SRAM (IDT’s latest, no change last three years) 18Mb ZBT (max 200MHz) 512K x 36 1M x 18 18Mb QDRII (max 250MHz) 512K x 36 1M x 18

© Derek Chiou & Mattan Erez 32 “Experimental” Memory Technology Not yet mainstream, but making headway Embedded DRAM DRAM in logic process, integrated with the processor In between SRAM and DRAM in terms of properties STT-RAM – Spin torque transfer RAM Based on Spintronics – manipulation of electron spins Works like 60’s “core memory”, but nano-sized “best of all worlds”, but still low density and experimental PC-RAM – Phase-change RAM Based on heat-related changes to physical structure of cell FLASH replacement May replace DRAM

© Derek Chiou & Mattan Erez 33 Memories of Specific Generation store the same number of bits Capacity = Height * Width * #Banks SDRAM (1Gb) 32M x 4 x 8 banks 16M x 8 x 8 banks 8M x 16 x 8 banks As RAM output gets wider, RAM height gets shorter Same number of bits per RAM! 32M x4 16M x8 8M x16

© Derek Chiou & Mattan Erez 34 Narrower RAMs Enable Greater Capacity Given Constant Total Width 8M x 16 32M x 4

© Derek Chiou & Mattan Erez 35 What If You Want More RAM Capacity? Go to smaller width RAMs Any problems? Additional capabilities? x1

© Derek Chiou & Mattan Erez 36 More Memory x8 8 8 addr MAR CE WE 0 logic x8 8 8 CE WE Any Problems?

© Derek Chiou & Mattan Erez 37 Separate CE x8 8 8 addr MAR CE WE 0 logic x8 8 8 CE WE 1

© Derek Chiou & Mattan Erez 38 Memory Modules (DIMMs) Dual In-line Memory Module (DIMM) Standard memory interface today Multiple chips on independent module Easy to build and maintain systems DIMMs have one or more “ranks” Rank is multiple chips that share same CE

© Derek Chiou & Mattan Erez 39 Memory Modules (DIMMs) Dual In-line Memory Module (DIMM) Standard memory interface today Multiple chips on independent module Easy to build and maintain systems DIMMs have one or more “ranks” Rank is multiple chips that share same CE x8 8 8 addr MAR CE WE 0 logic x8 8 8 CE WE 1 Width? Ranks? Chips/rank?