Corso di Sistemi in Tempo Reale Laurea in Ingegneria dell‘Automazione a.a. 2008-2009 Paolo Pagano

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Corso di Sistemi in Tempo Reale Laurea in Ingegneria dell‘Automazione a.a Paolo Pagano

Paolo Pagano - Embedded Systems2/13 Today’s topic First day (23 rd ) –Basics of FSM (slides by prof. Lipari) –The Uppaal platform –Formal verification

Paolo Pagano - Embedded Systems3/13 Finite State Machines Credits: John Favaro

Paolo Pagano - Embedded Systems4/13 Finite State Machines

Paolo Pagano - Embedded Systems5/13 Finite State Machines

Paolo Pagano - Embedded Systems6/13 Finite State Machines

Paolo Pagano - Embedded Systems7/13 Finite State Machines

Paolo Pagano - Embedded Systems8/13 Uppaal model Uppaal ( is a tool box for validation (via graphical simulation) and verification (via automatic model-checking) of FSM driven systems. It consists of two main parts: –a graphical user interface; –a model-checker engine.

Paolo Pagano - Embedded Systems9/13 FSM design and implementation We model a panel of leds and buttons making use of a set of FSMs; Let’s verify this simple system making use of Uppaal inner engine. States Transitions Conditions

Paolo Pagano - Embedded Systems10/13 Formal verification (1/2)

Paolo Pagano - Embedded Systems11/13 Modeling OS-entities like Mutexes

Paolo Pagano - Embedded Systems12/13 Formal verification (2/2)