© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e Chapter 15 Bus Interface Barry B. Brey

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e ISA Bus The Industry Standard Architecture (ISA) bus was the first I/O bus found on the original PC. This bus operated at 8 MHz and was 8-bits wide. Through enhancement it was increased to a 16- bit bus. Although seldom found in personal computers, it is still found in industrial applications and probably will remain in them for years to come.

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e S2S1U3U4U5U6 On 0300H0301H0302H0303H OnOff0304H0305H0306H0307H OffOn0308H0309H030AH030BH Off 030CH030DH030EH030FH

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e library ieee; use ieee.std_logic_1164.all; entity DECODER_15_3 is port ( IOW, A14, A13, A12, A11, A10, A9, A8, A7, A6 A5, A4, A3, A2, A1, A0, S1, S2: in STD_LOGIC; U3, U4, U5, U6: out STD_LOGIC ); end; architecture V1 of DECODER_15_3 is begin U3 <= IOW or A14 or A13 or A12 or A11 or A10 or not A9 or not A8 or A7 or A6 or A5 or A4 or A1 or A0 or (S2 or S1 or A3 or A2) and (S2 or not S1 or A3 or not A2) and (not S2 or S1 or not A3 or A2) and (not S2 or not S1 or not A3 or not A2); U4 <= IOW or A14 or A13 or A12 or A11 or A10 or not A9 or not A8 or A7 or A6 or A5 or A4 or A1 or not A0 or (S2 or S1 or A3 or A2) and (S2 or not S1 or A3 or not A2) and (not S2 or S1 or not A3 or A2) and (not S2 or not S1 or not A3 or not A2); U5 <= IOW or A14 or A13 or A12 or A11 or A10 or not A9 or not A8 or A7 or A6 or A5 or A4 or not A1 or A0 or (S2 or S1 or A3 or A2) and (S2 or not S1 or A3 or not A2) and (not S2 or S1 or not A3 or A2) and (not S2 or not S1 or not A3 or not A2); U6 <= IOW or A14 or A13 or A12 or A11 or A10 or not A9 or not A8 or A7 or A6 or A5 or A4 or not A1 or not A0 or (S2 or S1 or A3 or A2) and (S2 or not S1 or A3 or not A2) and (not S2 or S1 or not A3 or A2) and (not S2 or not S1 or not A3 or not A2); end V1;

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e void OutPort(int address, int data) { _asm { mov edx,address mov eax,data mov ecx,4 OutPort1: out dx,al;output 8-bits shr eax,8;get next 8-bit section inc dx;address next port loop OutPort1;repeat 4 times }

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e void OutPrt(int address, int data) { for ( int a = address; a < address + 4; a++ ) { _asm { mov edx,a mov eax,data out dx,al } data >>= 8;//get next 8-bit section }

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e library ieee; use ieee.std_logic_1164.all; entity DECODER_15_4 is port ( IOW, IOR, A9, A8, A7, A6 A5, A4, A3, A2, A1, A0: in STD_LOGIC; A, B, C, D, E, F: out STD_LOGIC ); end; architecture V1 of DECODER_15_4 is begin A <= not A9 or not A8 or A7 or A6 or A5 or A4 or A3 or A2 or A1 or A0 or IOR; B <= not A9 or not A8 or A7 or A6 or A5 or A4 or A3 or A2 or A1 or A0 or IOW; C <= not A9 or not A8 or A7 or A6 or A5 or A4 or A3 or A2 or A1 or not A0 or IOR; D <= not A9 or not A8 or A7 or A6 or A5 or A4 or A3 or A2 or not A1 or not A0 or IOR; E <= not A9 or not A8 or A7 or A6 or A5 or A4 or A3 or A2 or not A1 or A0 or IOR; F <= not A9 or not A8 or A7 or A6 or A5 or A4 or A3 or A2 or not A1 or A0 or IOW; end V1;

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e DevicePort Start ADC (U3)0300H Read ADC (U3)0300H Read INTR (U3)0301H Start ADC (U4)0302H Read SDC (U4)0302H Read INTR (U4)0303H

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e char ADC(int address) { char temp = 1; if ( address ) address = 2; address += 0x300; _asm {;start converter mov edx,address out dx,al } while ( temp )//wait if busy { _asm { mov edx,address inc edx in al,dx mov temp,al and al,1 } _asm {;get data mov edx,address in al,dx mov temp,al } return temp; }

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e The Parallel Port The parallel port is a legacy device that was at one time used to send data to printers. Most printers today are USB devices because of the reduced cost of the cable. Parallel can sustain data rates that approach 500 MBps.

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e MOV AL,20H MOV DX,37AH OUT DX,AL MOV DX,378H IN AL,DX MOV DX,378H MOV AL,WRITE_DATA OUT DX,AL

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e Serial Data The COM ports on a PC are used for serial data communications. There are up to 8 of them available, but most modern systems use only one called COM1. Some systems also contain a second COM2 port.

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e bool WriteComPort(CString PortSpecifier, CString data) { DCB dcb; DWORD byteswritten; HANDLE hPort = CreateFile(PortSpecifier, GENERIC_WRITE, 0, NULL, OPEN_EXISTING, 0, NULL); if (!GetCommState(hPort,&dcb)){ return false; } dcb.BaudRate = CBR_9600;//9600 Baud dcb.ByteSize = 8;//8 data bits dcb.Parity = NOPARITY;//no parity dcb.StopBits = ONESTOPBIT;//1 stop if (!SetCommState(hPort,&dcb)) return false; bool retVal = WriteFile(hPort,data,1,&byteswritten,NULL); CloseHandle(hPort);//close the handle return retVal; }

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e int ReadByte(CString PortSpecifier) { DCB dcb; int retVal; BYTE Byte; DWORD dwBytesTransferred; DWORD dwCommModemStatus; HANDLE hPort = CreateFile(PortSpecifier, GENERIC_READ, 0, NULL, OPEN_EXISTING, 0, NULL); if (!GetCommState(hPort,&dcb)) return 0x100; dcb.BaudRate = CBR_9600;//9600 Baud dcb.ByteSize = 8;//8 data bits dcb.Parity = NOPARITY;//no parity dcb.StopBits = ONESTOPBIT;//1 stop if (!SetCommState(hPort,&dcb)) return 0x100; SetCommMask (hPort, EV_RXCHAR | EV_ERR);//receive character event WaitCommEvent (hPort, &dwCommModemStatus, 0);//wait for character if (dwCommModemStatus & EV_RXCHAR) ReadFile (hPort, &Byte, 1, &dwBytesTransferred, 0); //read 1 else if (dwCommModemStatus & EV_ERR) retVal = 0x101; retVal = Byte; CloseHandle(hPort); return retVal; }

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e USB The universal serial bus (USB) transfers data at rates of between 1Mbps to 480 Mbps depending on the interface standard available. The USB bus has become a very common way to interface many I/O device to the personal computer.

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e PIDNameTypeDescription E1OUTToken Host  function transaction D2ACKHandshakeReceiver accepts packet C3Data0DataData packet (PID even) A5SOFTokenStart of frame 69INToken Function  host transaction 5ANAKHandshakeReceiver does not accept packet 4BData1DataData packet (PID odd) 3CPRESpecialHost preamble 2DSetupTokenSetup command 1EStallTokenStalled

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e