COMPUTER GRAPHICS CS 482 – FALL 2014 NOVEMBER 10, 2014 GRAPHICS HARDWARE GRAPHICS PROCESSING UNITS PARALLELISM

GRAPHICS PROCESSING UNITS CS 482 – FALL 2014 HISTORICAL CONTEXT NOVEMBER 10, 2014: GRAPHICS HARDWAREPAGE 265 EARLY 1990’S VGA CONTROLLERS ALSO KNOWN AS A “GRAPHICS ACCELERATORS”, A VIDEO GRAPHICS ARRAY CONTROLLER COMBINED A MEMORY CONTROLLER AND A DISPLAY GENERATOR WITH ATTACHED DRAM. THESE CONTROLLERS CONTAINED FIXED FUNCTION CAPABILITIES FOR TRIANGULATION, RASTERIZATION, AND TEXTURE MAPPING. EARLY 2000’S FIRST GPUS WITH INCREASED PROCESSING POWER BEING DEMANDED, ESPECIALLY BY THE GAME INDUSTRY, CHIP DEVELOPERS BEGAN ADDING ENOUGH TO GPUS TO RIVAL THAT IN CPUS. THE FIXED FUNCTION CAPABILITIES WERE EXTENDED TO INCLUDE TRANSFORMATIONS, LIGHTING, AND SHADING. EARLY 2010’S MODERN GPUS FIXED FUNCTION DEDICATED LOGIC ON THESE CHIPS WAS REPLACED BY PROGRAMMABLE PROCESSORS. INTEGER ARITHMETIC WAS REPLACED WITH FLOATING- POINT ARITHMETIC. PARALLELISM WAS VASTLY INCREASED ON THE CHIPS. INSTRUCTIONS AND MEMORY BEGAN TO BE ADDED TO ALLOW GPUS TO BE USED FOR GENERAL PURPOSE PROGRAMMING, NOT JUST GRAPHICS.

GRAPHICS PROCESSING UNITS CS 482 – FALL 2014 DISTINGUISHING FEATURES NOVEMBER 10, 2014: GRAPHICS HARDWAREPAGE 266 AS INSTRUCTION SETS AND MEMORY EXPAND ON GPUS, THEY BECOME INCREASINGLY CAPABLE OF GENERAL PURPOSE PROCESSING, BUT THERE ARE STILL IMPORTANT DIFFERENCES BETWEEN GPUS AND CPUS. GPU INSTRUCTION SETS ARE STILL RATHER NARROWLY DEFINED, FOCUSING ON GRAPHICS ACCELERATIO N. GPU PROGRAMMING INTERFACES ARE HIGH- LEVEL APIS LIKE OPENGL AND DIRECTX, TOGETHER WITH HIGH- LEVEL SHADING LANGUAGES LIKE CG (C FOR GRAPHICS) AND HLSL (HIGH LEVEL SHADER LANGUAGE). THESE ARE SUPPORTED BY COMPILERS THAT GENERATE INTERMEDIATE LANGUAGES, WHICH ARE OPTIMIZED BY THE SPECIFIC GPU DRIVER SOFTWARE THAT GENERATES THE GPU’S MACHINE INSTRUCTIONS. GPU PROGRAMMING INTERFACES ARE HIGH- LEVEL APIS LIKE OPENGL AND DIRECTX, TOGETHER WITH HIGH- LEVEL SHADING LANGUAGES LIKE CG (C FOR GRAPHICS) AND HLSL (HIGH LEVEL SHADER LANGUAGE). THESE ARE SUPPORTED BY COMPILERS THAT GENERATE INTERMEDIATE LANGUAGES, WHICH ARE OPTIMIZED BY THE SPECIFIC GPU DRIVER SOFTWARE THAT GENERATES THE GPU’S MACHINE INSTRUCTIONS. GRAPHICS PROCESSING INVOLVES MANY STAGES OF OPERATIONS, SUCH AS VERTEX SHADING, GEOMETRY SHADING, RASTERIZATION, AND FRAGMENT SHADING, WHICH ARE PERFORMED ON A MASSIVELY PARALLEL SCALE IN A PIPELINED FASHION. VERTICES CAN BE DRAWN INDEPENDENTLY AND FRAGMENTS CAN BE RENDERED INDEPENDENTLY, ALLOWING COMPUTATION TO TAKE PLACE ALONG MANY PARALLEL THREADS OF CONTROL, RELYING ON THOSE THREADS TO HIDE LATENCY RATHER THAN RELYING ON CACHES TO AVOID LATENCY.

PARALLELISM CS 482 – FALL 2014 PARALLEL RENDERING NOVEMBER 10, 2014: GRAPHICS HARDWAREPAGE 267 FRAME BUFFER RASTER PROCESSORS GEOMETRY PROCESSORS WHEN RENDERING WAS HANDLED BY SERIAL PROCESSING MANAGED BY THE CPU, GRAPHICAL PRIMITIVES WERE PERIODICALLY FED TO A GPU, BUT MODERN PROGRAMMERS MUST ADDRESS THE PARALLELISM OF MULTIPLE CPUS AND GPUS. OBJECTS MAY BE SUBMITTED TO THE FRAME BUFFER IN ANY ORDER, BUT THEY MUST BE SORTED AS A LAST STEP BEFORE RASTERIZATION FOR TWO REASONS: TRANSPARENT OBJECTS NEED TO BE DRAWN BACK-TO- FRONT SO ANYTHING BEHIND A TRANSPARENT OBJECT SHOWS THROUGH. GPU STATE CHANGES (UPLOADING TEXTURES, ACTIVATING LIGHTING, ETC.) CAN BE EXPENSIVE, SO SORTING ALL SIMILAR STATES TOGETHER (EVERYTHING WITH THE SAME TEXTURE, THINGS THAT ARE LIT, ETC.), MINIMIZES STATE CHANGES, AND THE GPU TAKES LESS TIME TO RENDER THE SCENE. IN GENERAL, A MULTIPROCESSOR-BASED PARALLEL PIPELINE DISTRIBUTES GEOMETRY AMONG SEVERAL PROCESSORS, WHOSE RESULTS MUST ULTIMATELY BE GATHERED TOGETHER INTO THE FRAME BUFFER. DATABASE

PARALLELISM CS 482 – FALL 2014 SORT-FIRST MULTIPROCESSOR-BASED ARCHITECTURE NOVEMBER 10, 2014: GRAPHICS HARDWAREPAGE 268 FRAME BUFFER RASTER PROCESSORS GEOMETRY PROCESSORS DATABASE SUBDIVIDE THE FRAME BUFFER INTO TILES THAT ARE MAPPED TO THE AVAILABLE PROCESSORS, DISTRIBUTING PRIMITIVES TO PROCESSORS BASED UPON THEIR TILES. COUPLE EACH GEOMETRY PROCESSOR WITH A RASTERIZER TO FORM A COMPLETE RENDERING UNIT. P1P1 P2 P3 P4 1.SUBDIVIDE THE SCREEN P1:P2:P3:P4: ADVANTAGE: THIS ARCHITECTURE CAN EXPLOIT FRAME-TO-FRAME COHERENCE, REDISTRIBUTING PRIMITIVES TO PROCESSORS ONLY WHEN THEY MOVE BETWEEN SCREEN REGIONS. 2.“PRE-TRANSFORM” THE PRIMITIVES INTO SCREEN COORDINATES VIA BOUNDING BOXES 3.DISTRIBUTE THE PRIMITIVES 4.EACH PROCESSOR RENDERS ITS OWN PRIMITIVES 5.NO COMMUNICATION NEEDED AFTERWARDS DISADVANTAGE: IT IS SUSCEPTIBLE TO LOAD IMBALANCES SINCE SOME PORTIONS OF THE SCREEN MAY HAVE MANY MORE THINGS TO RENDER THAN OTHER PORTIONS.

PARALLELISM CS 482 – FALL 2014 SORT-MIDDLE MULTIPROCESSOR-BASED ARCHITECTURE NOVEMBER 10, 2014: GRAPHICS HARDWAREPAGE 269 FRAME BUFFER RASTER PROCESSORS GEOMETRY PROCESSORS DATABASE PRIMITIVES ARE TRANSFORMED INTO SCREEN COORDINATES, SORTED BY REGION, AND ROUTED FROM GEOMETRY PROCESSORS TO RASTERIZERS, WHICH RENDER THEIR REGION. FRAGMENTS ARE THEN COLLECTED AND ASSEMBLED INTO THE FRAME BUFFER. P1: 1.ARBITRARY ASSIGNMENT P2: P3: P4: P1: P3: RASTERIZATION ADVANTAGE: IN THIS ARCHITECTURE, GEOMETRY CAN BE DISTRIBUTED AMONG PROCESSORS WITHOUT REGARD TO THE SUBDIVISION OF THE SCREEN. P1P1 P2 P3 P4 P2: P4: DISADVANTAGE: POOR LOAD DISTRIBUTION - SOME AREAS OF SCREEN MAY BE RELATIVELY EMPTY. DISADVANTAGE: LATENCY - ALL PROCESSORS MUST FINISH BEFORE FINAL IMAGE IS COMPOSED. DISADVANTAGE: ORDER- DEPENDENT PRIMITIVES (SUCH AS TRANSPARENT OBJECTS) ARE DIFFICULT TO ACCOMMODATE SINCE FRAGMENTS ARRIVE FOR PROCESSING IN NONDETERMINISTIC ORDER. 2.GEOMETRY PROCESSING 3.SORTING

PARALLELISM CS 482 – FALL 2014 SORT-LAST MULTIPROCESSOR-BASED ARCHITECTURE NOVEMBER 10, 2014: GRAPHICS HARDWAREPAGE 270 FRAME BUFFER RASTER PROCESSORS GEOMETRY PROCESSORS DATABASE RENDERERS ARE RESPONSIBLE FOR RENDERING A FULL-SCREEN IMAGE USING THEIR SHARE OF THE PRIMITIVES. EACH PROCESSOR IS ASSIGNED A SHARE OF THE PRIMITIVES AND RENDERS THEM AS A COMPLETE SCENE. ADVANTAGE: NO REQUIREMENT TO SORT OR REDISTRIBUTE PRIMITIVES; EACH RENDERER COMPUTES ITS IMAGE AS IF IT WERE THE ONLY RENDERER IN THE SYSTEM. THE PARTIAL IMAGES ARE COMPOSITED TOGETHER, TAKING INTO ACCOUNT THE DISTANCE OF EACH PIXEL IN EACH LAYER FROM THE CAMERA, WHICH GUARANTEES THAT THE RESULTS OF THE INDIVIDUAL RENDERERS ARE LAYERED CORRECTLY. P1P1 P2P3P4 P1P1 P2P3P4 DISADVANTAGE: IT REQUIRES A HIGH BANDWIDTH IMAGE COMPOSITOR. EACH PROCESSOR IS ASSIGNED A SECTOR’S PORTION OF THE SUB-SCENES AND SORTS THE IMAGES WITH Z- COMPOSITING/Z- BUFFER