Chapter 4 I/O Port Programming

Objective 我們要瞭解 8051 的各個腳位（pins）的意義與用法，才能知道 8051 是如何與外界溝通。 8051 的一些特別的 pins：Vcc...。 8051 提供 4 組 I/O ports：P0～P3 以送出資料與接收資料。 如何寫程式控制 I/O ports。 利用 Appendix C 瞭解為什麼控制 8051 的 I/O ports 需要這樣的限制。 然後就可以設計 8051 的軟硬體系統。

Sections 4.1 Pin description of the 8051 4.2 I/O programming; bit manipulation

Section 4.1 Pin Description of the 8051

Packing Types of 8051 The 8051 family members come in different packages, such as DIP（dual in-line package）,QFP（quad flat package）and LLC（leadless chip carrier）. See Appendix H（Pages 427-429） They all have 40 pins. Figure 4-1. 8051 Pin Diagram

Figure 4-1. 8051 Pin Diagram 8051 (8031) PDIP/Cerdip 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST (RXD)P3.0 (TXD)P3.1 (T0)P3.4 (T1)P3.5 XTAL2 XTAL1 GND (INT0)P3.2 (INT1)P3.3 (RD)P3.7 (WR)P3.6 Vcc P0.0(AD0) P0.1(AD1) P0.2(AD2) P0.3(AD3) P0.4(AD4) P0.5(AD5) P0.6(AD6) P0.7(AD7) EA/VPP ALE/PROG PSEN P2.7(A15) P2.6(A14) P2.5(A13) P2.4(A12) P2.3(A11) P2.2(A10) P2.1(A9) P2.0(A8) 8051 (8031)

Pins of 8051（1/4） Vcc（pin 40）： GND（pin 20）：ground Vcc provides supply voltage to the chip. The voltage source is +5V. GND（pin 20）：ground XTAL1 and XTAL2（pins 19,18）： These 2 pins provide external clock. Way 1：using a quartz crystal oscillator  Way 2：using a TTL oscillator  Example 4-1 shows the relationship between XTAL and the machine cycle. 

Pins of 8051（2/4） RST（pin 9）：reset It is an input pin and is active high（normally low）. The high pulse must be high at least 2 machine cycles. It is a power-on reset. Upon applying a high pulse to RST, the microcontroller will reset and all values in registers will be lost. Reset values of some 8051 registers  Way 1：Power-on reset circuit  Way 2：Power-on reset with debounce 

Pins of 8051（3/4） /EA（pin 31）：external access There is no on-chip ROM in 8031 and 8032 . The /EA pin is connected to GND to indicate the code is stored externally. /PSEN ＆ ALE are used for external ROM. For 8051, /EA pin is connected to Vcc. “/” means active low. /PSEN（pin 29）：program store enable This is an output pin and is connected to the OE pin of the ROM. See Chapter 14.

Pins of 8051（4/4） ALE（pin 30）：address latch enable I/O port pins It is an output pin and is active high. 8051 port 0 provides both address and data. The ALE pin is used for de-multiplexing the address and data by connecting to the G pin of the 74LS373 latch. I/O port pins The four ports P0, P1, P2, and P3. Each port uses 8 pins. All I/O pins are bi-directional.

Figure 4-2 (a). XTAL Connection to 8051 Using a quartz crystal oscillator We can observe the frequency on the XTAL2 pin. C2 30pF C1 XTAL2 XTAL1 GND 

Figure 4-2 (b). XTAL Connection to an External Clock Source Using a TTL oscillator XTAL2 is unconnected. NC EXTERNAL OSCILLATOR SIGNAL XTAL2 XTAL1 GND 

Example 4-1  Find the machine cycle for (a) XTAL = 11.0592 MHz (b) XTAL = 16 MHz. Solution: (a) 11.0592 MHz / 12 = 921.6 kHz; machine cycle = 1 / 921.6 kHz = 1.085 s (b) 16 MHz / 12 = 1.333 MHz; machine cycle = 1 / 1.333 MHz = 0.75 s 

Table 4-1: RESET Value of Some 8051 Registers PC 0000 ACC 0000 B 0000 PSW 0000 SP 0007 DPTR 0000 RAM are all zero. 

Figure 4-3 (a). Power-On RESET Circuit Vcc + 10 uF 31 EA/VPP X1 30 pF 19 11.0592 MHz 8.2 K X2 18 30 pF RST 9 

Figure 4-3 (b). Power-On RESET with Debounce Vcc 31 EA/VPP X1 10 uF 30 pF X2 RST 9 8.2 K 

Pins of I/O Port The 8051 has four I/O ports Port 0 （pins 32-39）：P0（P0.0～P0.7） Port 1（pins 1-8）：P1（P1.0～P1.7） Port 2（pins 21-28）：P2（P2.0～P2.7） Port 3（pins 10-17）：P3（P3.0～P3.7） Each port has 8 pins. Named P0.X （X=0,1,...,7）, P1.X, P2.X, P3.X Ex：P0.0 is the bit 0（LSB）of P0 Ex：P0.7 is the bit 7（MSB）of P0 These 8 bits form a byte. Each port can be used as input or output (bi-direction). Program is to read data from P0 and then send data to P1

Port 1（pins 1-8） Port 1 is denoted by P1. P1.0 ~ P1.7 We use P1 as examples to show the operations on ports. P1 as an output port (i.e., write CPU data to the external pin) P1 as an input port (i.e., read pin data into CPU bus)

A Pin of Port 1 P0.x 8051 IC Read latch Vcc TB2 Load(L1) P1.X pin D Q Clk Q Vcc Load(L1) Read latch Read pin Write to latch Internal CPU bus M1 P1.X pin P1.X TB1 TB2 P0.x 8051 IC

Hardware Structure of I/O Pin Each pin of I/O ports Internal CPU bus：communicate with CPU A D latch store the value of this pin D latch is controlled by “Write to latch” Write to latch＝1：write data into the D latch 2 Tri-state buffer： TB1: controlled by “Read pin” Read pin＝1：really read the data present at the pin TB2: controlled by “Read latch” Read latch＝1：read value from internal latch A transistor M1 gate Gate=0: open Gate=1: close

Figure C-9. Tri-state Buffer Output Input Tri-state control (active high) L L H H Low Highimpedance (open-circuit) H H 

Writing “1” to Output Pin P1.X D Q Clk Q Vcc Load(L1) Read latch Read pin Write to latch Internal CPU bus M1 P1.X pin P1.X TB2 2. output pin is Vcc 1. write a 1 to the pin 1 output 1 TB1 8051 IC

Writing “0” to Output Pin P1.X D Q Clk Q Vcc Load(L1) Read latch Read pin Write to latch Internal CPU bus M1 P1.X pin P1.X TB2 2. output pin is ground 1. write a 0 to the pin output 0 1 TB1 8051 IC

Port 1 as Output（Write to a Port） Send data to Port 1： MOV A,#55H BACK: MOV P1,A ACALL DELAY CPL A SJMP BACK Let P1 toggle. You can write to P1 directly.

Reading Input v.s. Port Latch When reading ports, there are two possibilities： Read the status of the input pin. （from external pin value） MOV A, PX JNB P2.1, TARGET ; jump if P2.1 is not set JB P2.1, TARGET ; jump if P2.1 is set Figures C-11, C-12 Read the internal latch of the output port. ANL P1, A ; P1 ← P1 AND A ORL P1, A ; P1 ← P1 OR A INC P1 ; increase P1 Figure C-17 Table C-6 Read-Modify-Write Instruction (or Table 8-5) See Section 8.3

Figure C-11. Reading “High” at Input Pin D Q Clk Q Vcc Load(L1) Read latch Read pin Write to latch Internal CPU bus M1 P1.X pin P1.X 2. MOV A,P1 external pin=High TB2 write a 1 to the pin MOV P1,#0FFH 1 1 TB1 3. Read pin=1 Read latch=0 Write to latch=1 8051 IC

Figure C-12. Reading “Low” at Input Pin D Q Clk Q Vcc Load(L1) Read latch Read pin Write to latch Internal CPU bus M1 P1.X pin P1.X 2. MOV A,P1 external pin=Low TB2 write a 1 to the pin MOV P1,#0FFH 1 TB1 3. Read pin=1 Read latch=0 Write to latch=1 8051 IC

Port 1 as Input（Read from Port） In order to make P1 an input, the port must be programmed by writing 1 to all the bit. MOV A,#0FFH ;A=11111111B MOV P1,A ;make P1 an input port BACK: MOV A,P1 ;get data from P0 MOV P2,A ;send data to P2 SJMP BACK To be an input port, P0, P1, P2 and P3 have similar methods. Program is to read data from P0 and then send data to P1

Table 8-4: Instructions For Reading an Input Port Following are instructions for reading external pins of ports: Mnemonics Examples Description MOV A,PX MOV A,P2 Bring into A the data at P2 pins JNB PX.Y,.. JNB P2.1,TARGET Jump if pin P2.1 is low JB PX.Y,.. JB P1.3,TARGET Jump if pin P1.3 is high MOV C,PX.Y MOV C,P2.4 Copy status of pin P2.4 to CY

Figure C-17. Reading the Latch 1. Read pin=0 Read latch=1 Write to latch=0 (Assume P1.X=0 initially) D Q Clk Q Vcc Load(L1) Read latch Read pin Write to latch Internal CPU bus M1 P1.X pin P1.X TB2 2. CPU compute P1.X OR 1 4. P1.X=1 1 1 3. write result to latch Read pin=0 Read latch=0 Write to latch=1 TB1 8051 IC

Reading Latch Exclusive-or the Port 1： MOV P1,#55H ;P1=01010101 ORL P1,#0F0H ;P1=11110101 1. The read latch activates TB2 and bring the data from the Q latch into CPU. Read P1.0=0 2. CPU performs an operation. This data is ORed with bit 1 of register A. Get 1. 3. The latch is modified. D latch of P1.0 has value 1. 4. The result is written to the external pin. External pin (pin 1: P1.0) has value 1.

Read-modify-write Feature Read-modify-write Instructions Table C-6 This features combines 3 actions in a single instruction： 1. CPU reads the latch of the port 2. CPU perform the operation 3. Modifying the latch 4. Writing to the pin Note that 8 pins of P1 work independently.

Port 1 as Input（Read from latch） Exclusive-or the Port 1： MOV P1,#55H ;P1=01010101 AGAIN: XOR P1,#0FFH ;complement ACALL DELAY SJMP AGAIN Note that the XOR of 55H and FFH gives AAH. XOR of AAH and FFH gives 55H. The instruction read the data in the latch (not from the pin). The instruction result will put into the latch and the pin. P1 is configured as an output port.

Table C-6：Read-Modify-Write Instructions Mnemonics Example SETB P1.4 SETB PX.Y CLR P1.3 CLR PX.Y MOV P1.2,C MOV PX.Y,C DJNZ P1,TARGET DJNZ PX, TARGET INC P1 INC CPL P1.2 CPL JBC P1.1, TARGET JBC PX.Y, TARGET XRL P1,A XRL ORL P1,A ORL ANL P1,A ANL DEC P1 DEC ANL: Latch data AND with A , then save back to latch and write to the external pin ORL: OR XRL: XOR JBC: jump to TARGET if bit set and clear bit CPL: complement INC: increase DEC: decrease DJNZ: decrease P1 and jump if P1 not zero MOV the latch value to carry CLR: clear bit, SETB: set bit

Questions How to write the data to a pin？ How to read the data from the pin？ Read the value present at the external pin. Why we need to set the pin first？ Read the value come from the latch（not from the external pin）. Why the instruction is called read-modify write?

Other Pins P1, P2, and P3 have internal pull-up resisters. P1, P2, and P3 are not open drain. P0 has no internal pull-up resistors and does not connects to Vcc inside the 8051. P0 is open drain. Compare the figures of P1.X and P0.X.  However, for a programmer, it is the same to program P0, P1, P2 and P3. All the ports upon RESET are configured as output.

A Pin of Port 0 P1.x 8051 IC Read latch TB2 P0.X pin Internal CPU bus D Q Clk Q Read latch Read pin Write to latch Internal CPU bus M1 P0.X pin P1.X TB1 TB2 P1.x 8051 IC

Port 0（pins 32-39） P0 is an open drain. Open drain is a term used for MOS chips in the same way that open collector is used for TTL chips. When P0 is used for simple data I/O we must connect it to external pull-up resistors. Each pin of P0 must be connected externally to a 10K ohm pull-up resistor. With external pull-up resistors connected upon reset, port 0 is configured as an output port. Open drain is a term used for MOS chips in the same way that open collector is used for TTL chips.

Figure 4-4. Port 0 with Pull-Up Resistors DS5000 8751 8951 Vcc 10 K Port 0

Dual Role of Port 0 When connecting an 8051/8031 to an external memory, the 8051 uses ports to send addresses and read instructions. 8031 is capable of accessing 64K bytes of external memory. 16-bit address：P0 provides both address A0-A7, P2 provides address A8-A15. Also, P0 provides data lines D0-D7. When P0 is used for address/data multiplexing, it is connected to the 74LS373 to latch the address. There is no need for external pull-up resistors as shown in Chapter 14.

Figure 14-9 74LS373 8051 ROM 74LS373 ALE P0.0 P0.7 PSEN A0 A7 D0 D7 OE OC EA G 8051 ROM

2. 74373 latches the address and send to ROM Reading ROM (1/2) 2. 74373 latches the address and send to ROM 1. Send address to ROM D 74LS373 ALE P0.0 P0.7 PSEN A0 A7 D0 D7 P2.0 P2.7 A8 A12 OE OC EA G 8051 ROM Address

Reading ROM (2/2) 2. 74373 latches the address and send to ROM D 74LS373 ALE P0.0 P0.7 PSEN A0 A7 D0 D7 P2.0 P2.7 A8 A12 OE OC EA G 8051 ROM Address 3. ROM send the instruction back

ALE Pin The ALE pin is used for de-multiplexing the address and data by connecting to the G pin of the 74LS373 latch. When ALE=0, P0 provides data D0-D7. When ALE=1, P0 provides address A0-A7. The reason is to allow P0 to multiplex address and data.

Port 2（pins 21-28） Port 2 does not need any pull-up resistors since it already has pull-up resistors internally. In an 8031-based system, P2 are used to provide address A8-A15.

Port 3（pins 10-17） Port 3 does not need any pull-up resistors since it already has pull-up resistors internally. Although port 3 is configured as an output port upon reset, this is not the way it is most commonly used. Port 3 has the additional function of providing signals. Serial communications signal：RxD, TxD（Chapter 10） External interrupt：/INT0, /INT1（Chapter 11） Timer/counter：T0, T1（Chapter 9） External memory accesses in 8031-based system：/WR, /RD（Chapter 14）

Table 4-2: Port 3 Alternate Functions 17 RD P3.7 16 WR P3.6 15 T1 P3.5 14 T0 P3.4 13 INT1 P3.3 12 INT0 P3.2 11 TxD P3.1 10 RxD P3.0 Pin Function P3 Bit

Section 4.2 I/O Programming; Bit Manipulation

I/O Programming To toggle every bit of P1 continuously. 3 ways：Way 1, Way 2, and Way 3. Which one is better？

Way 1 Send data to Port 1 through ACC： BACK: MOV A,#55H ;A=01010101B MOV P1,A ACALL DELAY MOV A,#0AAH ;A=10101010B SJMP BACK

Way 2 Access Port 1 directly： BACK: MOV P1,#55H ;P1=01010101B ACALL DELAY MOV P1,#0AAH ;P1=10101010B SJMP BACK

Way 3 Read-modify-write feature： MOV P1,#55H ;P1=01010101B AGAIN: XRL P1,#0FFH ACALL DELAY SJMP AGAIN The instruction XRL P1,#0FFH do EX-OR P1 and FFH （That is, to toggle P1.）

Bit Manipulation Sometimes we need to access only 1 or 2 bits of the port instead of the entire 8 bits. Table 4-3 shows how to name each pin for each I/O port.  Example 4-2  See Section 8.1 single-bit instruction programming

Table 4-3: Single-Bit Addressability of Ports Port Bit P3 P2 P1 P0 

Example 4-2 Write a program to perform the following. (a) Keep monitoring the P1.2 bit until it becomes high, (b) When P1.2 becomes high, write value 45H to port 0, and (c) Send a high-to-low (H-to-L) pulse to P2.3. Solution: SETB P1.2 ;make P1.2 an input MOV A,#45H ;A=45H AGAIN:JNB P1.2,AGAIN;get out when P.2=1 MOV P0,A ;issue A to P0 SETB P2.3 ;make P2.3 high CLR P2.3 ;make P2.3 low for H-to-L Note： 1. JNB: jump if no bit（jump if P1.2 = 0 ） 2. a H-to-L pulse by the sequence of instructions SETB and CLR.

You are able to Explain the purpose of each pin of the 8051 microcontroller List the 4 ports of the 8051 Describe the dual role of port 0 in providing both data and address Code Assembly language to use the ports for input or output Explain the use of port 3 for interrupt signals Code 8051 instructions for I/O handling Code bit-manipulation instructions in the 8051

Homework Chapter 4 Problems：12,28,31,33,34,38,40 Note: Questions of “True and false” need your explanation. Please write and compile the program of Problems 28,38,40.