Hierarchical Floorplanning of Chip Multiprocessors using Subgraph Discovery Javier de San Pedro Jordi Cortadella Antoni Roca Universitat Politècnica de.

Slides:

Advertisements

Similar presentations

Analysis of Floorplanning Algorithm in EDA Tools

Advertisements

THERMAL-AWARE BUS-DRIVEN FLOORPLANNING PO-HSUN WU & TSUNG-YI HO Department of Computer Science and Information Engineering, National Cheng Kung University.

ICS’02 UPC An Interleaved Cache Clustered VLIW Processor E. Gibert, J. Sánchez * and A. González * Dept. d’Arquitectura de Computadors Universitat Politècnica.

gSpan: Graph-based substructure pattern mining

© 2013 IBM Corporation Use of Hierarchical Design Methodologies in Global Infrastructure of the POWER7+ Processor Brian Veraa Ryan Nett.

Buffer and FF Insertion Slides from Charles J. Alpert IBM Corp.

1 Advancing Supercomputer Performance Through Interconnection Topology Synthesis Yi Zhu, Michael Taylor, Scott B. Baden and Chung-Kuan Cheng Department.

Ch.7 Layout Design Standard Cell Design TAIST ICTES Program VLSI Design Methodology Hiroaki Kunieda Tokyo Institute of Technology.

Congestion Driven Placement for VLSI Standard Cell Design Shawki Areibi and Zhen Yang School of Engineering, University of Guelph, Ontario, Canada December.

Structural Web Search Using a Graph-Based Discovery System Nitish Manocha, Diane J. Cook, and Lawrence B. Holder University of Texas at Arlington

Discovering Substructures in Chemical Toxicity Domain Masters Project Defense by Ravindra Nath Chittimoori Committee: DR. Lawrence B. Holder, DR. Diane.

Prénom Nom Document Analysis: Segmentation & Layout Analysis Prof. Rolf Ingold, University of Fribourg Master course, spring semester 2008.

1 Logic synthesis from concurrent specifications Jordi Cortadella Universitat Politecnica de Catalunya Barcelona, Spain In collaboration with M. Kishinevsky,

Graph-Based Concept Learning Jesus A. Gonzalez, Lawrence B. Holder, and Diane J. Cook Department of Computer Science and Engineering University of Texas.

Register Allocation (via graph coloring). Lecture Outline Memory Hierarchy Management Register Allocation –Register interference graph –Graph coloring.

Processing Rate Optimization by Sequential System Floorplanning Jia Wang 1, Ping-Chih Wu 2, and Hai Zhou 1 1 Electrical Engineering & Computer Science.

Chip Planning 1. Introduction Chip Planning:  Deals with large modules with −known areas −fixed/changeable shapes −(possibly fixed locations for some.

1 ENTITY test is port a: in bit; end ENTITY test; DRC LVS ERC Circuit Design Functional Design and Logic Design Physical Design Physical Verification and.

Paging for Multi-Core Shared Caches Alejandro López-Ortiz, Alejandro Salinger ITCS, January 8 th, 2012.

1 The VAMPIR and PARAVER performance analysis tools applied to a wet chemical etching parallel algorithm S. Boeriu 1 and J.C. Bruch, Jr. 2 1 Center for.

11 Multi-Product Floorplan Optimization Framework for Chip Multiprocessors Marco Escalante 1, Andrew B. Kahng 2, Michael Kishinevsky 1, Umit Ogras 3 and.

Dynamic Runtime Testing for Cycle-Accurate Simulators Saša Tomić, Adrián Cristal, Osman Unsal, Mateo Valero Barcelona Supercomputing Center (BSC) Universitat.

Using Abstraction to Speed Up Search Robert Holte University of Ottawa.

Design methodology.

Physical Planning for the Architectural Exploration of Large-Scale Chip Multiprocessors Javier de San Pedro, Nikita Nikitin, Jordi Cortadella and Jordi.

1 SUBSTRUCTURE DISCOVERY IN REAL WORLD SPATIO-TEMPORAL DOMAINS Jesus A. Gonzalez Supervisor:Dr. Lawrence B. Holder Committee:Dr. Diane J. Cook Dr. Lynn.

Logic Synthesis for Low Power(CHAPTER 6) 6.1 Introduction 6.2 Power Estimation Techniques 6.3 Power Minimization Techniques 6.4 Summary.

Efficient Data Mining for Calling Path Patterns in GSM Networks Information Systems, accepted 5 December 2002 SPEAKER: YAO-TE WANG ( 王耀德 )

An Efficient Clustering Algorithm For Low Power Clock Tree Synthesis Rupesh S. Shelar Enterprise Microprocessor Group Intel Corporation, Hillsboro, OR.

A NEW ECO TECHNOLOGY FOR FUNCTIONAL CHANGES AND REMOVING TIMING VIOLATIONS Jui-Hung Hung, Yao-Kai Yeh,Yung-Sheng Tseng and Tsai-Ming Hsieh Dept. of Information.

Massachusetts Institute of Technology 1 L14 – Physical Design Spring 2007 Ajay Joshi.

A Graph Based Algorithm for Data Path Optimization in Custom Processors J. Trajkovic, M. Reshadi, B. Gorjiara, D. Gajski Center for Embedded Computer Systems.

Combinational Problems: Unate Covering, Binate Covering, Graph Coloring and Maximum Cliques Example of application: Decomposition.

L11: Lower Power High Level Synthesis(2) 성균관대학교 조 준 동 교수

Physical Synthesis Ing. Pullini Antonio

Layout-Driven Test-Architecture Design and Optimization for 3D SoCs under Pre-Bond Test- Pin-Count Constraint Li Jiang 1, Qiang Xu 1, Krishnendu Chakrabarty.

1 Discovering Robust Knowledge from Databases that Change Chun-Nan HsuCraig A. Knoblock Arizona State UniversityUniversity of Southern California Journal.

Frequent Subgraph Discovery Michihiro Kuramochi and George Karypis ICDM 2001.

Configurable Multi-product Floorplanning Qiang Ma, Martin D.F. Wong, Kai-Yuan Chao ASP-DAC 2010.

EE 466/586 VLSI Design Partha Pande School of EECS Washington State University

6. A PPLICATION MAPPING 6.3 HW/SW partitioning 6.4 Mapping to heterogeneous multi-processors 1 6. Application mapping (part 2)

1 CS612 Algorithms for Electronic Design Automation CS 612 – Lecture 1 Course Overview Mustafa Ozdal Computer Engineering Department, Bilkent University.

System-level power analysis and estimation September 20, 2006 Chong-Min Kyung.

DEVICES AND DESIGN : ASIC. DEFINITION Any IC other than a general purpose IC which contains the functionality of thousands of gates is usually called.

Simultaneous Analog Placement and Routing with Current Flow and Current Density Considerations H.C. Ou, H.C.C. Chien and Y.W. Chang Electronics Engineering,

1 Lic Presentation Memory Aware Task Assignment and Scheduling for Multiprocessor Embedded Systems Radoslaw Szymanek / Embedded System Design

Routability-driven Floorplanning With Buffer Planning Chiu Wing Sham Evangeline F. Y. Young Department of Computer Science & Engineering The Chinese University.

By P.-H. Lin, H. Zhang, M.D.F. Wong, and Y.-W. Chang Presented by Lin Liu, Michigan Tech Based on “Thermal-Driven Analog Placement Considering Device Matching”

Power Analysis of Embedded Software : A Fast Step Towards Software Power Minimization 指導教授 : 陳少傑教授組員 : R 張馨怡 R 林秀萍.

System in Package and Chip-Package-Board Co-Design

VLSI Floorplanning and Planar Graphs prepared and Instructed by Shmuel Wimer Eng. Faculty, Bar-Ilan University July 2015VLSI Floor Planning and Planar.

Dirk Stroobandt Ghent University Electronics and Information Systems Department A New Design Methodology Based on System-Level Interconnect Prediction.

Intelligent Database Systems Lab 國立雲林科技大學 National Yunlin University of Science and Technology 1 Mining Advisor-Advisee Relationships from Research Publication.

Routing Wire Optimization through Generic Synthesis on FPGA Carry Hadi P. Afshar Joint work with: Grace Zgheib, Philip Brisk and Paolo Ienne.

Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 15: March 13, 2013 High Level Synthesis II Dataflow Graph Sharing.

On the Ability of Graph Coloring Heuristics to Find Substructures in Social Networks David Chalupa By, Tejaswini Nallagatla.

Specification mining for asynchronous controllers Javier de San Pedro† Thomas Bourgeat ‡ Jordi Cortadella† † Universitat Politecnica de Catalunya ‡ Massachusetts.

Ning Jin, Wei Wang ICDE 2011 LTS: Discriminative Subgraph Mining by Learning from Search History.

Partial Reconfigurable Designs

Unsupervised Learning: Clustering

Unsupervised Learning: Clustering

Asynchronous Interface Specification, Analysis and Synthesis

Kristof Blutman† , Hamed Fatemi† , Andrew B

Reactive Clocks with Variability-Tracking Jitter

Patterns extraction from process executions

Area Between Two Curves

Jordi Cortadella and Jordi Petit

Architectural-Level Synthesis

ICS 252 Introduction to Computer Design

Parallelized Analytic Placer

Presentation transcript:

Hierarchical Floorplanning of Chip Multiprocessors using Subgraph Discovery Javier de San Pedro Jordi Cortadella Antoni Roca Universitat Politècnica de Catalunya (Barcelona) Graph-TA 20141

Outline Introduction – Chip multiprocessors and floorplanning Hierarchical floorplanning methodology Results and conclusions Graph-TA 20142

What is a Chip Multiprocessor? Graph-TA Off-Chip Memory CoreCore L3 Cache CoreCoreCoreCoreCoreCore Interconnect L2 Cache L1 Cache L2 Cache L1 Cache L2 Cache L1 Cache L2 Cache RouterRouter RouterRouterRouterRouterRouterRouter RouterRouter RouterRouter

What is floorplanning? Graph-TA MC CC L2L2 CC L2L2 L3L3 RingRing CC L2L2 CC L2L2 RR

Minimizing wire length Graph-TA CC L2L2 CC L2L2 CC L2L2 CC L2L2 rrrr rrrr rr rr RR L3L3

Maximizing regularity Graph-TA Reusability Design closure Reduce floorplanning cost

Finding repeating subgraphs Frequent subgraph discovery: Graph-TA Subdue: D. J. Cook and L. B. Holder, Graph-Based Data Mining, IEEE Intelligent Systems, 15(2), pages 32-41, 2000.

Example Graph-TA CC L2L2 CC L2L2 CC L2L2 CC L2L2 rrrr rrrr rr rr RR L3L3 1.Find candidate pattern The most repeated subgraph

Floorplanning a pattern Graph-TA CC L2L2 rr 1.Find repeated pattern 2.Floorplan pattern CC L2L2rr L2L2 CC L2L2 rr CC L2L2L2L2 L2L2L2L2rr Multiple floorplans are generated for a single pattern CCL2L2rr L2L2 CC L2L2rr L2L2 CC L2L2 rr CC L2L2L2L2 L2L2L2L2rr CCL2L2rr L2L2 All pareto-optimal floorplans efficiently stored as a bounding curve:

Creating hierarchy Graph-TA CC L2L2 CC L2L2 CC L2L2 CC L2L2 rrrr rrrr rr rr RR L3L3 1.Find candidate pattern 2.Floorplan pattern 3.Treat instances of pattern as black-boxes P1P1 P1P1 P1P1 P1P1 P1P1 CC L2L2 rr P1 is a new component type Has multiple shapes (defined by its bounding curve)

Hierarchical floorplanning Graph-TA rr rr RR L3L3 1.Find candidate pattern 2.Floorplan pattern 3.Treat instances of pattern as black-boxes 4.Repeat until no more patterns can be found P1P1 P1P1 P1P1 P1P1 P2P2 P2P2 P1P1 CC L2L2 rr P2P2 P1P1P1P1

Final floorplan Floorplanning the last pattern obtains the bounding curve for the entire chip Graph-TA RR L3L3 rrrr P2P2 P2P2 RR L3L3 rrrr P2P2 P2P2P2P2 RR L3L3 rr rr P2P2 P2P2

Generating multiple results Graph-TA RR L3L3 rrrr P2P2 P2P2 RR L3L3 rrrr P1P1P1P1 P1P1 P1P1 CC L2L2rr L2L2 CC L2L2rr L2L2 CC rr L2L2 L2L2 CC rr L2L2 L2L2 RR L3L3 rrrr CC L2L2rr L2L2 CC L2L2rr L2L2 CC rr L2L2 L2L2 CC rr L2L2 L2L2 RR L3L3 rrrr CC L2L2rr L2L2 CC L2L2rr L2L2 CC rr L2L2 L2L2 CC rr L2L2 L2L2 RR L3L3 rrrr

Example: ring of rings Graph-TA

Example: ring of rings Graph-TA

Graph-TA Estimated wirelength (meters)

Conclusions We can extract regularity from a netlist and build regular floorplans – Competitive area, wire length results – Reduce design time Future: application to other domains – High-level synthesis, logic synthesis, … Graph-TA