Shift Registers Module M11.1 Section 7.3.

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Presentation transcript:

Shift Registers Module M11.1 Section 7.3

4-Bit Shift Register

shift4.abl MODULE Shift4 TITLE '4-bit Shift Register A. Student, 7/22/02' DECLARATIONS " INPUT PINS " PB PIN 10; " push-button switch (clock) Clear PIN 7; " Switch 2 Load PIN 11; " Switch 3 data_in PIN 70; " Switch 8 " OUTPUT PINS " Q3..Q0 PIN 39,37,36,35 ISTYPE 'reg buffer'; " LED 5..8 Q = [Q3..Q0]; " 3-bit output vector

shift4.abl (cont’d) EQUATIONS Q.c = PB; Q0.d = !Clear & data_in; Q1.d = !Clear & Q0; Q2.d = !Clear & Q1; Q3.d = !Clear & Q2; END Shift4

CUPL Simulation File 4shift.si

CUPL Simulation File 4shift.si

CUPL Simulation Output File

Ring Counter

ring4.abl MODULE Ring4 TITLE '4-bit Ring Counter A. Student, 7/22/02' DECLARATIONS " INPUT PINS " PB PIN 10; " push-button switch (clock) Clear PIN 7; " Switch 2 " OUTPUT PINS " Q3..Q0 PIN 39,37,36,35 ISTYPE 'reg buffer'; " LED 5..8 Q = [Q3..Q0]; " 3-bit output vector

ring4.abl (cont’d) EQUATIONS Q.c = PB; Q0.d = !Clear & Q3; Q3.d = !Clear & Q2 # Clear; END Ring4

CUPL Simulation File ring4.si

CUPL Simulation File ring4.si

CUPL Simulation Output File

Ring Counter

Johnson Counter

Exercise Detect input sequence 1101 din fsm clk dout clr din dout 1 0 1 1 0 1 1 0 1 0 0 1 1 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0

Use Shift Register dout 1 1 1 din Q0 Q1 Q2 Q3 CLK D Q D Q D Q D Q CLK 1 1 din Q0 Q1 Q2 Q3 D Q D Q D Q D Q CLK !Q CLK !Q CLK !Q CLK !Q CLK

Lab 8 Johnson Counter & Random Number Generator CLK D Q !Q Q3 Q2 Q1 Q0 Random Number Generator

Q3 Q2 Q1 Q0 0 0 0 1 1 1 0 0 0 8 1 1 0 0 C 1 1 1 0 E 1 1 1 1 F 0 1 1 1 7 1 0 1 1 B 0 1 0 1 5 Q3 Q2 Q1 Q0 1 0 1 0 A 1 1 0 1 D 0 1 1 0 6 0 0 1 1 3 1 0 0 1 9 0 1 0 0 4 0 0 1 0 2 0 0 0 1 1