Chap. 6 Dataflow Modeling

Dataflow Modeling Continuous Assignments Delays Expressions, Operators and Operands Operator Types Examples Summary

Continuous Assignments - I Assign a logic value to a wire/net Syntax Continuous_assign::= assign [drive_strength] [delay] list_of_assignments; List_of_net_assignments::=net_assignment{, net_assignment} Net_assignment::=net_lvalue = expression Default drive_strength: strong1 or strong0 Delay: propagation time from inputs to output

Continuous Assignments - II Constraints LHS of assignment (=) must be scalar net or vector net (rather than reg or vector reg) Once the value of RHS expression changes, the value of assigned wire also changes accordingly The expression of RHS can be reg, wire or function Delay controls the update time of LHS when the value of RHS has changed like gate delay

An Example of Continuous Assignments

Implicit Continuous Assignment Perform a wire assignment when declaring the wire wire out; assign out = in1 & in2; (equals the following) wire out = in1 & in2;

Implicit Net Declaration Perform assignment for an un-declared wire wire i1, i2; assign out = i1 & i2; // wire out has not been // declared

Dataflow Modeling Continuous Assignments Delays Expressions, Operators and Operands Operator Types Examples Summary

Delays Regular Assignment Delay Implicit Continuous Assignment Delay Net Declaration Delay

Regular Assignment Delay assign #10 out = in1 & in2;

Implicit Continuous Assignment Delay wire #10 out = in1 & in2; (equals the following) wire out; assign #10 out = in1 & in2;

Net Declaration Delay wire #10 out; assign out = in1 & in2; (equals the following) wire out; assign #10 out = in1 & in2;

Dataflow Modeling Continuous Assignments Delays Expressions, Operators and Operands Operator Types Examples Summary

Expressions Combine operator and operand to output a result a^b addr1[20:17] + addr2[20:17] in1 | in2

Operands Data type － constants, integers, real, nets, registers, times, bit-select, part-select, memory or function calls Integer count, final_count; final_count = count + 1; real a, b, c; c = a – b; reg [15:0] reg1, reg2; reg [3:0] reg_out; reg_out = reg1[3:0] ^ reg2[3:0]; reg ret_value; ret_value = calculate_parity(A, B);

Operators Perform an operation on operands d1 && d2 // && operates on operands d1 and d2 !a[0] B1>>1

Dataflow Modeling Continuous Assignments Delays Expressions, Operators and Operands Operator Types Examples Summary

Operator Classes Arithmetic Logical Relational Equality Bitwise Reduction Shift Concatenation Conditional

Operation Types - I

Operator Types - II

Arithmetic Operators - I Binary Operator (+, -, *, /, **, %) A = 4’b0011; B = 4’b0100; D = 6; E = 4; A * B D / E A + B B – A F = E ** F;

Arithmetic Operators - II Binary Operator (+, -, *, /, **, %) in1 = 4’b101x; in2 = 4’b1010; sum = in1 + in2; // sum is 4’bx 13 % 3 16 % 4 -7 % 2 7 % -2 Unary Operator (+, -) -4 +5

Logical Operators &&(logic-and), ||(logic-or), !(logic-not) A = 3; B = 0; A && B A || B !A !B A = 2’0x; B = 2’b10; ( a == 2) && (b == 3)

Relational Operators >, <, <=, >= A = 4, B = 3 X = 4’b1010, Y = 4’b1101, Z = 4’b1xxx A <= B A > B Y >= X Y < Z

Equality Operators - I Logic Equality (==, !=) Event Equality (===, !==)

Equality Operators - II A = 4, B = 3 X = 4’b1010, Y = 4’b1101 Z = 4’b1xxz, M = 4’b1xxz, N = 4’b1xxx A == B // 0 X != Y // 1 X == Z // x Z === M // 1 Z === N // 0 M !=== N // 1

Bitwise Operators - I ~(Negation), & (and), | (or), ^ (xor), ^~ (xnor)

Bitwise Operators - II X = 4’b1010, Y = 4’b1101, Z = 4’b10x1 X & Y // 4’b1000 X | Y // 4’b1111 X ^ Y // 4’b0111 X ^~ Y // 4’b1000 X & Z // 4’b10x0 X = 4’b1010, Y = 4’b0000 X | Y // 4’b1010 X || Y // 1

Reduction Operator &, ~&, |, ~|, ^, ~^ X = 4’b1010 &X // 1’b0 ^X // 1’b0, can be used to count even parity

Shift Operator >>(right shift), <<(left shift), >>>(arithmetic right shift), <<< X = 4’b1100 Y = X >> 1; // 4’b0110 Y = X << 1; // 4’b1000 Y = X << 2; // 4’b0000 Integer a, b, c; a = 0; b = -10; c = a + (b >>> 3);

Concatenation Operator {, } A = 1’b1, B = 2’b00, C = 2’b10, D = 3’b110 Y = { B, C } Y = { A, B, C, D, 3’b001 } Y = { A, B[0], C[1] }

Replication Operator reg A; reg [1:0] B, C; reg [2:0] D; A = 1’b1; B = 2’b00; C = 2’b10; D = 3’b110; Y = {4{A}} Y = {4{A}, 2{B}} Y = {4{A}, 2{B}, C}

Conditional Operator Condition_expr ? ture_expr : false_expr; assign addr_bus = drive_enable ? Addr_out : 36’bz; assign out = control ? in1 : in0; Assign out = ( A == 3 ) ? ( control ? x : y ) : ( control ? m : n );

Operator Precedence

Dataflow Modeling Continuous Assignments Delays Expressions, Operators and Operands Operator Types Examples Summary

Design 4-to-1 Multiplexer Using logic expression Using conditional operator

Using Logic Expression

Using Conditional Operator

Design 4-bit Full Adder Using addition (+) and concatenation ({, }) Carry look ahead

Using Addition and Concatenation Operator (DataFlow Modeling)

Carry Look Ahead Full Adder - I

Carry Look Ahead Full Adder - II

4-bit Ripple Carry Counter

Negative Triggered D Flip-Flop with Clear

4-bit Ripple Carry Counter in Verilog

T Flip-Flop in Verilog

D Flip-Flop in Verilog

Testbench for 4-bit Ripple Counter - I

Testbench for 4-bit Ripple Counter - I

Simulation Result

Dataflow Modeling Continuous Assignments Delays Expressions, Operators and Operands Operator Types Examples Summary

Summary Continuous Assignment (expression, operator and operand) Define delays in continuous assignment Various operators in Verilog Arithmetic, logical, relational, equality, bitwise, reduction, shift, concatenation, replication, conditional Conditional operator is equivalent to “if-then-else” statement