Advanced ITC Presentation A. Pogiel J. Rajski J. Tyszer.

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Presentation transcript:

Advanced ITC Presentation A. Pogiel J. Rajski J. Tyszer

2 Motivation  volume reduction higher than scan chains / channels ratio  high observability of scan cells for wide range of X-profiles  design simplicity  minimum control information Reliable test response compactor

3 Outline  EDT environment  Compactor architecture  Unknown states  Scan chain selection  Experimental results  Fault diagnosis  Conclusions

4 EDT architecture Compacted responses Compressed patterns  X-control  Scan  Deterministic patterns  Embedded test  Selective compaction  Direct diagnosis

5 Linear selector

6 Synthesis algorithm  Generate randomly a polynomial  Verify sharing of mask bits  Determine rank  Repeat 1÷3 for several polynomials  Accept poly with the highest rank  Repeat 1÷5 for all outputs

7 Linear independence DAC 2001 specified bits 32 mask bits New

8 Encoding efficiency mask bits Scan chains:

9 Diagnostic resolution Design Xs % No comp. X-PressDifference Fail ratio D D D D D D Overdrive: single stuck-at faults selected randomly The smallest mask register

10 Conclusions  Compression higher than scan chains / channels ratio  Programmable scan selector  High observability of scan errors  Immune to high X-fill rates  Proven on industrial designs

Dariusz Czysz, Janusz Rajski, Jerzy Tyszer

12 purpose Low power scheme compatible with test compression reduced switching during all scan operations preserved test quality accelerated scan shifting

13 outline  EDT environment  Low power test architecture  Scan shift-in operations  Power aware decompressor  Capture and scan shift-out  Experimental results  Conclusions

14 motivation 100 scan chains Scan chains observing faults Test patterns 0.9M gates 45K scan cells

15 control data encoding  Constants provided on a per pattern basis  Asserting all variables turn off low power test  0 1 c 1 + c 3 + c 7 = 0 c 2 + c 4 + c 7 = 1 c 3 + c 5 + c 6 = 0 c n c n-1 … c 2 c 1 c 0

16 clock gater control data Design Specified bits per cube Gated FFs by one cube FFs per specified bit FFs with gated clocks (%) D D D D Average Specified bits refer to bits provided by scan to shut off flip-flops

17 experimental results – filling chains D1D2D3D4 WTM [%] LoadUnload Capture Constant Shadow register Combined WSA [%]

18 filling chains & clock gating D1D2D3D4 Reduction [%] Load Unload Capture Capture – only clock gaters

19 conclusions  EDT can deliver low power tests  No impact on quality  Significant reduction of test power in shift  Flexible trade-offs –power efficiency –compression –test application time