2/16/09 Lab 3 Jorge Crichigno. 2/16/09 Half-adder.

Slides:

Advertisements

Similar presentations

UNIT 2: Data Flow description

Advertisements

1 Introduction to VHDL (Continued) EE19D. 2 Basic elements of a VHDL Model Package Declaration ENTITY (interface description) ARCHITECTURE (functionality)

1 Statements. 2 Statements - 강의순서 ▣ 병행 (Concurrent) Statement ◈ Concurrent Signal Assignment, Simple ◈ Concurrent Signal Assignment, Conditional ◈ Concurrent.

Synchronous Sequential Logic

Hardware Description Language (HDL)

Lecture 6 Chap 8: Sequential VHDL Instructors: Fu-Chiung Cheng ( 鄭福炯 ) Associate Professor Computer Science & Engineering Tatung University.

Instructor: Yuzhuang Hu Course Website The first lab is ready. The first assignment will be released.

9/18/08 Lab 2 - Solution TA: Jorge. 9/18/08 Half-adder.

Why Behavioral Wait statement Signal Timing Examples of Behavioral Descriptions –ROM.

VHDL Intro What does VHDL stand for? VHSIC Hardware Description Language VHSIC = Very High Speed Integrated Circuit Developed in 1982 by Govt. to standardize.

Kazi Fall 2006 EEGN 4941 EEGN-494 HDL Design Principles for VLSI/FPGAs Khurram Kazi Some of the slides were taken from K Gaj’s lecture slides from GMU’s.

HDL-Based Digital Design Part I: Introduction to VHDL (I) Dr. Yingtao Jiang Department Electrical and Computer Engineering University of Nevada Las Vegas.

Hardware Description Language HDL. 2 Hardware Description Language HDL  Describes circuits and systems in text. −As a software program.  Can be processed.

VHDL. What is VHDL? VHDL: VHSIC Hardware Description Language  VHSIC: Very High Speed Integrated Circuit 7/2/ R.H.Khade.

Today’s Lecture Process model –initial & always statements Assignments –Continuous & procedural assignments Timing Control System tasks.

each of these is an instantiation of “full_adder”

Introduction to VHDL (part 2)

Advanced FPGA Based System Design Lecture-9 & 10 VHDL Sequential Code By: Dr Imtiaz Hussain 1.

ECE 332 Digital Electronics and Logic Design Lab Lab 5 VHDL Design Styles Testbenches.

Modeling styles: 1. Structural Modeling: As a set of interconnected components (to represent structure), 2. Dataflow Modeling: As a set of concurrent assignment.

IAY 0600 Digitaalsüsteemide disain Event-Driven Simulation Alexander Sudnitson Tallinn University of Technology.

Sequential Statements

Languages for HW and SW Development Ondrej Cevan.

1 Workshop Topics - Outline Workshop 1 - Introduction Workshop 2 - module instantiation Workshop 3 - Lexical conventions Workshop 4 - Value Logic System.

2-Jun-16EE5141 Chapter 3 ä The concept of the signal ä Process concurrency ä Delta time ä Concurrent and sequential statements ä Process activation by.

Introduction to VLSI Design – Lec01. Chapter 1 Introduction to VLSI Systems Lecture # 6 Computer-Aided Design Technology for VLSI.

Copyright(c) 1996 W. B. Ligon III1 Getting Started with VHDL VHDL code is composed of a number of entities Entities describe the interface of the component.

Fall 2004EE 3563 Digital Systems Design EE 3563 VHSIC Hardware Description Language  Required Reading: –These Slides –VHDL Tutorial  Very High Speed.

IAY 0600 Digital Systems Design VHDL discussion Verification: Testbenches Alexander Sudnitson Tallinn University of Technology.

Timing Model VHDL uses the following simulation cycle to model the stimulus and response nature of digital hardware Start Simulation Update Signals Execute.

Assignment write a short notes on 1.Manufacturing Testing. 2.Functional Testing. 3.Files and Text I/O. 4.Differentiate the cpld and fpga architecture.

VHDL – Behavioral Modeling and Registered Elements ENGIN 341 – Advanced Digital Design University of Massachusetts Boston Department of Engineering Dr.

CSCI-365 Computer Organization Lecture Note: Some slides and/or pictures in the following are adapted from: Computer Organization and Design, Patterson.

Apr. 3, 2000Systems Architecture I1 Introduction to VHDL (CS 570) Jeremy R. Johnson Wed. Nov. 8, 2000.

Relational Operators Result is boolean: greater than (>) less than (=) less than or equal to (

IAY 0600 Digital Systems Design Event-Driven Simulation VHDL Discussion Alexander Sudnitson Tallinn University of Technology.

May 9, 2001Systems Architecture I1 Systems Architecture I (CS ) Lab 5: Introduction to VHDL Jeremy R. Johnson May 9, 2001.

COE 202 Introduction to Verilog Computer Engineering Department College of Computer Sciences and Engineering King Fahd University of Petroleum and Minerals.

IAY 0600 Digital Systems Design VHDL discussion Verification: Testbenches Alexander Sudnitson Tallinn University of Technology.

Interacting Finite State Machine Design Shaun Murphy.

Lecture #12 Page 1 ECE 4110– Digital Logic Design Lecture #12 Agenda 1.VHDL : Behavioral Design (Processes) Announcements 1.n/a.

Instructor: Oluwayomi Adamo Digital Systems Design.

Introduction to Verilog COE 202 Digital Logic Design Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals.

ECE 4110–5110 Digital System Design

ECE 3130 Digital Electronics and Design

Systems Architecture Lab: Introduction to VHDL

IAY 0600 Digitaalsüsteemide disain

HDL simulation and Synthesis (Marks16)

Behavioral Style Combinational Design with VHDL

IAY 0600 Digital Systems Design

Verification: Testbenches in Combinational Design

‘if-else’ & ‘case’ Statements

Timing Model Start Simulation Delay Update Signals Execute Processes

Behavioral Style Combinational Design with VHDL

IAY 0600 Digital Systems Design

ECE 434 Advanced Digital System L08

VHDL VHSIC Hardware Description Language VHSIC

Introduction to Verilog

IAS 0600 Digital Systems Design

Copyright Joanne DeGroat, ECE, OSU

IAS 0600 Digital Systems Design

VHDL Programming (08 Marks)

How do you achieve deterministic concurrent simulation.

Timing & Concurrency II

Copyright Joanne DeGroat, ECE, OSU

Timing & Concurrency II

Timing & Concurrency II

COE 202 Introduction to Verilog

Presentation transcript:

2/16/09 Lab 3 Jorge Crichigno

2/16/09 Half-adder

2/16/09 Half-adder Testbench

2/16/09 Waveform for half-adder simulation tb stimulus 10 ns testbench ha x_signal y_signal x y s c s_signal c_signal

2/16/09 Full-adder

2/16/09 Full-adder Testbench

2/16/09 Waveform for full-adder simulation tb testbench fa x_signal y_signal x y s c s_signal c_signal z_signal z

2/16/09 Process. Type of processes. Process with sensitivity list. Process with wait statement. Example. Sequential Signal Assignment Statement. Syntax. Examples. Pitfall. Intermediate value. Conceptual implementation Variables. Syntax. Intermediate value. Example. Conceptual implementation Case statement. Syntax. Example. Multiplexor. Conceptual implementation. Lab 3 - Sequential Statements

2/16/09 Process Contains a set of sequential statements to be executed sequentially The whole process is a concurrent statement Can be interpreted as a circuit part enclosed inside of a black box Two types: with sensitive list and with wait statement Lab 3 - Sequential Statements

2/16/09 A process with a sensitivity list Syntax process (sensitivity_list) declarations; begin sequential statement;... end process; Lab 3 - Sequential Statements

2/16/09 Lab 3 - Sequential Statements Process with sensitivity list. Interpretation: “black box, indivisible circuit part”. Sensitivity list The execution of the process is initiated whenever an event occurs on any of the signals in the sensitivity list For practical purposes, you can regards a process as a “big” concurrent signal assignment statement Note:

2/16/09 Waveform for Example Process not activated on B change

2/16/09 A Process With wait Statement Process has no sensitivity list Process continues the execution until a wait statement is reached and then suspended Forms of wait statement: –wait on signals; –wait until boolean_expression; –wait for time_expression;

2/16/09 Sequential Signal Assignment Statement Signal_name <= value_expression; Syntax: U 0 1 U 1 0 U 1 1 U undefined

2/16/09 Sequential Signal Assignment Statement If all assignments are within DELTA-delay, only the last assignment takes effect. You can think as the signals are not updated until the end of the process (i.e., it never assumes any “intermediate” value).

2/16/09 Variable Assignment Statement Variable_name := value_expression; Syntax: Used inside processes. The assignment takes effect “immediately”. Easy to understand, but not clear hardware mapping! Use signal always you can; rely on variables only for the characteristics that cannot be described by signals Note: Conceptual implementation

2/16/09 Case Statement Syntax: Example:

2/16/09 Introduction to Multiplexers Example of case statement: Multiplexor Truth Table

2/16/09 4-to-1 multiplexer – VHDL Implementation Entity ENTITY mux4x1 IS PORT ( S : IN STD_LOGIC_VECTOR (1 downto 0); D0 : IN STD_LOGIC; D1 : IN STD_LOGIC; D2 : IN STD_LOGIC; D3 : IN STD_LOGIC; Y : OUT STD_LOGIC ); END mux4x1; ARCHITECTURE multiplexor4x1 OF mux4x1 IS BEGIN PROCESS(S, D0, D1, D2, D3) BEGIN CASE S IS WHEN "00" => Y <= D0; WHEN "01" => Y <= D1; WHEN "10“ => Y <= D2; WHEN OTHERS => Y <= D3; END CASE; END PROCESS; END multiplexor4x1; Architecture