VLSI-SoC, Atlanta J. Dalmasso, ML Flottes, B. Rouzeyre CNRS/ Univ. Montpellier II France 1 17/10/2007

2 Introduction T1, W1T2 = T1/10, W2 = 10xW1T3 = T1/10, W3 = W1 DUT decompression

17/10/ Introduction T1, W1T2 = T1/10, W2 = 10xW1T3 ≥ T1/10, W3 = W1 DUT decompression

Introduction 17/10/ Scan enable Control CLK FSM W ATE Channels N Scan Chains SR Compression method  independent of the circuit netlist  independent of the test data  no specific test tool is needed  No impact on fault coverage XXXXX0XXXX1X

Introduction 17/10/ Scan enable Control CLK FSM W ATE Channels N Scan Chains SR Compression method  independent of the circuit netlist  independent of the test data  no specific test tool is needed  No impact on fault coverage  core test time may be affected

Compression at system level Problem Statement (test time optimization) Algorithm Experimental Results 17/10/ Outline

Compression at System level 17/10/ Test Access Mechanism = Test bus 1500 ready cores Partitioned test buses W Tam1 W Tam2 C5 C1 C2 C3 C4

W Tam1 W Tam2 C5 W ATE C4 C2 C3 C1 Compression at System level 17/10/ W Tam1 W Tam2 W ATE C1 C2 C3 C4 C5 Solution space

C4 C2 C3 C1 W Tam1 W Tam2 C5 W ATE Compression at System level 17/10/ W Tam1 W ATE1 W Tam3 W ATE3 W Tam2 W ATE2 C1 C4 C2 C3 C5 C1 C2 C3 C4 C5 W Tam1 W Tam2 W ATE Solution space

Problem Statement 17/10/ Inputs W ATE channels, W TAM bit width n Cores C i Problem Determine optimal number of sub-buses Determine compression ratio on every bus Core assignment/scheduling for minimal test time compression increases test parallelism but may increase individual test time

Algorithm Outer loop For each ATE channel partition For each compatible TAM partition Find best core assignment (the lowest total test time) If this assignment decreases global test time memorize architecture and its associated scheduling 17/10/200711

Algorithm Outer loop Inner loop For each ATE channel partition For each compatible TAM partition Find best core assignment (the lowest total test time) If this assignment decreases global test time memorize architecture and its associated scheduling Initial Solution Put each core on the smallest possible bus Compute test time Improvement Find bus Bi which has the longest test time For each core on Bi, For all other bus Bj ( j ≠ i ) move core from Bi to Bj Compute test time Move core C from Bi to Bj so that test time is smallest 17/10/200712

Core test time vs Compression 17/10/ Indentification: Test Time = (  / compression ratio) + 

Core test time vs Compression 17/10/ Indentification: Test Time = (  / compression ratio) + 

Experiment on a 16 cores SoC 17/10/ C5 C6 C7 C8 C1 C2 C3 C4 C13 C14 C15 C16 C9 C10 C11 C12 64 TAM 32 ATE

Solution space exploration 17/10/ p# conf.TAT Lines' parameters (W ATE-i / W TAM-i ) (16,16) / (16, 48) (8,9,15) / (14,16,34) (5,7,8,12) / (7,14,16,27) (5,5,7,7,8) / (6,12,14,16,16)

Experiment on a 16 cores SoC 17/10/ C9 C10 C7 C6 C1 C2 C3 C4 C16 C14 C12 C5 C11 5 C15 C13 C ATE=32 TAM=64 T3=57941 ATE=TAM=64 T1=55738 No Compression ATE=TAM=32 T2=127413

Data Compression for System testing Test width reduction is the primary goal higher test parallelism without ATE cost Method for exploring architectural solutions one compressor for all cores, one compressor per core, no compressor... independant of the compression technique Test time reduction > 50% 17/10/ Conclusion

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