Pipeline Exceptions & ControlCSCE430/830 Pipelining in MIPS MIPS architecture was designed to be pipelined –Simple instruction format (makes IF, ID easy)

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Presentation transcript:

Pipeline Exceptions & ControlCSCE430/830 Pipelining in MIPS MIPS architecture was designed to be pipelined –Simple instruction format (makes IF, ID easy) »Single-word instructions »Small number of instruction formats »Common fields in same place (e.g., rs, rt) in different formats –Memory operations only in lw, sw instructions (simplifies EX) –Memory operands aligned in memory (simplifies MEM) –Single value for Write-Back (limits forwarding) Pipelining is harder in CISC architectures

Pipeline Exceptions & ControlCSCE430/830 Pipelined Datapath with Control Signals

Pipeline Exceptions & ControlCSCE430/830 Next Step: Adding Control Basic approach: build on single-cycle control –Place control unit in ID stage –Pass control signals to following stages Later: extra features to deal with: –Data forwarding –Stalls –Exceptions

Pipeline Exceptions & ControlCSCE430/830 Control for Pipelined Datapath RegDst ALUOp[1:0] ALUSrc MemRead MemWrite Branch RegWrite MemtoReg

Pipeline Exceptions & ControlCSCE430/830 Control for Pipelined Datapath

Pipeline Exceptions & ControlCSCE430/830 Datapath and Control Unit

Pipeline Exceptions & ControlCSCE430/830 Tracking Control Signals - Cycle 1 LW

Pipeline Exceptions & ControlCSCE430/830 Tracking Control Signals - Cycle 2 SWLW

Pipeline Exceptions & ControlCSCE430/830 Tracking Control Signals - Cycle 3 ADDSWLW

Pipeline Exceptions & ControlCSCE430/830 Tracking Control Signals - Cycle 4 SUBADD SW LW 1 0 0

Pipeline Exceptions & ControlCSCE430/ ADD Tracking Control Signals - Cycle 5 SUB SW LW

Pipeline Exceptions & ControlCSCE430/830 Class Exercise Consider the following code segment 1. LW R1, 0(R4) 2. LW R2, 0(R5) 3. ADD R3, R1, R2 4. BNZ R3, L 5. LW R4, 100(R1) 6. LW R5, 100(R2) 7. SUB R3, R4, R5 8.L: SW R3, 50(R1) Assuming that there is no forwarding, zero testing is being resolved during ID, and registers can be written in the first half of the WB cycle and also be read in the send half of the same WB cycle, Question: identify the resources of various hazards in the above code sequence.

Pipeline Exceptions & ControlCSCE430/830 Class Exercise Consider the following code segment 1. LW R1, 0(R4) 2. LW R2, 0(R5) 3. ADD R3, R1, R2 4. BNZ R3, L 5. LW R4, 100(R1) 6. LW R5, 100(R2) 7. SUB R3, R4, R5 8.L: SW R3, 50(R1) Assuming that there is no forwarding, zero testing is being resolved during ID, and registers can be written in the first of the WB cycle and also be read in the send half of the same WB cycle, Question: identify the resources of various hazards in the above code sequence.

Pipeline Exceptions & ControlCSCE430/830 Class Exercise Consider the following code segment 1. LW R1, 0(R4) 2. LW R2, 0(R5) 3. ADD R3, R1, R2 4. BNZ R3, L 5. LW R4, 100(R1) 6. LW R5, 100(R2) 7. SUB R3, R4, R5 8.L: SW R3, 50(R1) Use compiler techniques to reshuffle/rewrite the code (without changing the meaning of the program) as to minimize data hazards as far as possible. Assume that no other general purpose registers other than those used in the code, are available.

Pipeline Exceptions & ControlCSCE430/830 Class Exercise Consider the following code segment 1. LW R1, 0(R4) 2. LW R2, 0(R5) 3. ADD R3, R1, R2 4. BNZ R3, L 5. LW R4, 100(R1) 6. LW R5, 100(R2) 7. SUB R3, R4, R5 8.L: SW R3, 50(R1) 1. LW R1, 0(R4) 2. LW R2, 0(R5) 3. LW R4, 100(R1) 4. LW R5, 100(R2) 5. ADD R3, R1, R2 6. BNZ R3, L 7. SUB R3, R4, R5 8.L: SW R3, 50(R1)