COMP381 by M. Hamdi 1 (Recap) Pipeline Hazards

COMP381 by M. Hamdi 2 I n s t r. O r d e r add r1,r2,r3 sub r4,r1,r3 and r6,r1,r7 or r8,r1,r9 xor r10,r1,r11 Reg ALU DMemIfetch Reg ALU DMemIfetch Reg ALU DMemIfetch Reg ALU DMemIfetch Reg ALU DMemIfetch Reg Time (clock cycles) IFID/RF EX MEM WB Data Hazard on r1

COMP381 by M. Hamdi 3 Read After Write (RAW) Instr J tries to read operand before Instr I writes it Caused by a “Dependence” (in compiler nomenclature). This hazard results from an actual need for communication. I: add r1,r2,r3 J: sub r4,r1,r3 Data Hazards

COMP381 by M. Hamdi 4 Write After Read (WAR) Instr J writes operand before Instr I reads it Called an “anti-dependence” by compiler writers. This results from reuse of the name “r1”. Can’t happen in MIPS 5 stage pipeline because: – All instructions take 5 stages, and – Reads are always in stage 2, and – Writes are always in stage 5 I: sub r4,r1,r3 J: add r1,r2,r3 K: mul r6,r1,r7 Data Hazards

COMP381 by M. Hamdi 5 Write After Write (WAW) Instr J writes operand before Instr I writes it. “Output dependence” by compiler writers This also results from the reuse of name “r1”. Can’t happen in MIPS 5 stage pipeline because: – All instructions take 5 stages, and – Writes are always in stage 5 Will see WAR and WAW in complicated pipelines I: sub r1,r4,r3 J: add r1,r2,r3 K: mul r6,r1,r7 Data Hazards

COMP381 by M. Hamdi 6 stall Stall: One Way to “Fix” a Data Hazard I n s t r. O r d e r add r1,r2,r3 ALU IM Reg DMReg sub r4,r1,r3 and r6,r7,r1 ALU IM Reg DMReg ALU IM Reg DMReg Can fix data hazard by waiting – stall – but affects throughput

COMP381 by M. Hamdi 7 Time (clock cycles) I n s t r. O r d e r add r1,r2,r3 sub r4,r1,r3 and r6,r1,r7 or r8,r1,r9 xor r10,r1,r11 Reg ALU DMemIfetch Reg ALU DMemIfetch Reg ALU DMemIfetch Reg ALU DMemIfetch Reg ALU DMemIfetch Reg Solution: Data Forwarding

COMP381 by M. Hamdi 8 MEM/WR ID/EX EX/MEM Data Memory ALU mux Registers NextPC Immediate mux HW Change for Forwarding

COMP381 by M. Hamdi 9 Yet Another Complication! I n s t r. O r d e r add r1,r1,r2 ALU IM Reg DMReg add r1,r1,r3 add r1,r1,r4 ALU IM Reg DMReg ALU IM Reg DMReg Another potential data hazard can occur when there is a conflict between the result of the WB stage instruction and the MEM stage instruction – which should be forwarded?

COMP381 by M. Hamdi 10 Time (clock cycles) I n s t r. O r d e r lw r1, 0(r2) sub r4,r1,r6 and r6,r1,r7 or r8,r1,r9 Reg ALU MemIF Reg IF ALU Mem Reg ALU Mem Reg ALU MemIF Reg Data Hazard Even with Forwarding Bubble

COMP381 by M. Hamdi 11 flush Forwarding with Load-use Data Hazards I n s t r. O r d e r lw r1,100(r2) sub r4,r1,r5 and r6,r1,r7 xor r4,r1,r5 or r8, r1, r9 ALU IF Reg DMWB ALU IF Reg DM ALU IF Reg DMWB ALU IF Reg DMWB ALU IF Reg DMWB ALU IF Reg DM WB sub r4,r1,r5 and r6,r1,r7 xor r4,r1,r5 or r8, r1, r9

COMP381 by M. Hamdi 12 Try producing fast code for a = b + c; d = e – f; assuming a, b, c, d,e, and f in memory. Slow code: LW Rb,b LW Rc,c ADD Ra,Rb,Rc SW a,Ra LW Re,e LW Rf,f SUB Rd,Re,Rf SWd,Rd Software Scheduling Fast code: LW Rb,b LW Rc,c LW Re,e ADD Ra,Rb,Rc LW Rf,f SW a,Ra SUB Rd,Re,Rf SWd,Rd Compiler optimizes for performance. Hardware checks for safety.